Which SystemVerilog builds without Vivado?

148 constructs, one probe each: the design and a tb.sv that prints PASS. Vivado supports 122 of them; 104 of those pass every stage here.

Every probe in test/sv goes through four stages in a folder that holds only its sources. test/sv/expect.tsv records what each stage does today, whether Vivado accepts the construct and the source for that; test/sv/run.sh fails on any difference, in both directions. Sources for Vivado: UG901 v2023.2 (chapter, table, page), UG953 v2022.2 (the 7-series primitive guide) and Vivado logs from public CS223 lab repos, where the student's module and signal names are replaced by a description. A forum is marked as a weak source.

What does each stage check?

rtl
simulation		The design and its tb.sv simulated with Icarus Verilog (dewfpga sim). Pass: exit 0 and the testbench printed PASS.
synth
synthesis		Yosys synthesis (dewfpga bit), with the whole Basys3_Master.xdc uncommented as in a lab folder. Pass: the netlist was written.
netlist
the netlist		That netlist written back as Verilog: the same tb.sv, simulated on it with Yosys' xilinx/cells_sim.v, prints PASS, and every output bit matches the RTL on the same inputs (test/sv/eqv.py). This stage checks what synthesis made, not place and route or the bitstream.
bit
the bitstream		The same dewfpga bit exits 0 and writes top.bit: place and route with nextpnr-xilinx, the timing check, the frames and the bitstream.

Which probes pass every stage?

114 of 148.

Which probes build a bitstream whose netlist check fails?

3 of 148.

Which probes stop before a bitstream?

30 of 148.

Which probes build, and fail only in simulation?

1 of 148.

An error code from one of these runs? Every code, with what you saw, why and the fix. What the chain cannot do yet, in the guide: section 8.