SystemVerilog probes · 46Vivado: unverified

continue in a for loop in always_comb (count of set bits)

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 Table 27 (p.287) lists only 'Jump statements: Not Recommended', which does not say what Vivado does with continue, and no other page names it. No Vivado log in the corpus (it has no continue)

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 165 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/46_continue.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [4:0] n;
  always_comb begin
    n = 0;
    for (int i = 0; i < 16; i++) begin
      if (!sw[i]) continue;   // skip the switches that are off
      n++;
    end
  end
  assign led = {11'b0, n};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i, b, c;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      c = 0; for (b = 0; b < 16; b = b + 1) c = c + sw[b];
      if (!(led === c)) begin $display("FAIL: continue, count of set bits (sw=%h led=%h want %0d)", sw, led, c); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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