SystemVerilog probes · 45Vivado: supported
break out of a for loop in always_comb (lowest set bit)
Vivado: supported. The open-source chain: all four stages pass.
| stage | today |
|---|---|
| rtl, simulation | pass |
| synth, synthesis | pass |
| netlist, the netlist | pass |
| bit, the bitstream | pass |
What does Vivado do with it?
Supported. UG901 v2023.2 Ch.10 'Loop Statements' (p.280): 'The forever loop executes all the time. To avoid infinite loops, use it with the break statement to get out of the loop.'; Table 27 (p.287): 'Jump statements: Not Recommended' (discouraged, not refused)
What does the open-source chain do with it?
since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 20 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'
What is the probe's code?
From test/sv/45_break.
design.sv
module top(input logic [15:0] sw, output logic [15:0] led);
logic [3:0] k; logic f;
always_comb begin
k = 0; f = 0;
for (int i = 0; i < 16; i++)
if (sw[i]) begin k = i; f = 1; break; end // stop at the lowest set switch
end
assign led = {11'b0, f, k};
endmodule
tb.sv
module tb;
reg clk = 1'b0;
reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
reg [15:0] sw = 16'h0000;
wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
initial begin #200000 $display("FAIL: timeout"); $finish; end
integer i, b, k;
top dut(.sw(sw), .led(led));
initial begin
for (i = 0; i < 65536; i = i + 1) begin
sw = i; #1
k = -1; for (b = 15; b >= 0; b = b - 1) if (sw[b]) k = b;
if (!(led === (k < 0 ? 16'd0 : {11'd0, 1'b1, 4'(k)}))) begin $display("FAIL: break, lowest set bit (sw=%h led=%h)", sw, led); $finish; end
end
$display("PASS"); $finish;
end
endmodule
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