SystemVerilog probes · 44Vivado: supported

SystemVerilog do ... while in always_comb, twice: a popcount, and a loop whose condition is false on entry (its body still runs once, which tells do-while from while)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Loop statements: Supported'; Ch.10 'Loop Statements' (p.280): 'The do-while loop performs the same function as the while loop, but instead it tests the expression after the statement.'

What does the open-source chain do with it?

yosys: syntax error at do (design.sv:7)

What is the probe's code?

From test/sv/44_do_while_loop.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [4:0] n;
  logic f;
  always_comb begin
    int i;
    n = 0; i = 0;
    do begin n = n + sw[i]; i++; end while (i < 16);   // the condition is tested after the body
    f = 1'b0; i = 16;
    do begin f = sw[i - 1]; i++; end while (i < 16);   // false on entry: the body still runs once
  end
  assign led = {10'b0, f, n};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i, b, c;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      c = 0; for (b = 0; b < 16; b = b + 1) c = c + sw[b];
      if (!(led === {10'b0, sw[15], 5'(c)})) begin $display("FAIL: do-while popcount, and a body that runs once (sw=%h led=%h want %0d, %b)", sw, led, c, sw[15]); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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