SystemVerilog probes · 43Vivado: supported

foreach over an unpacked array in always_comb

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Loop statements: Supported'; Ch.10 'Loop Statements' (p.280): 'The for-each loop executes a statement for each element in an array.'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 27 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/43_foreach_loop.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] n [0:3];
  always_comb foreach (n[i]) n[i] = sw[4*i +: 4] + 4'(i);   // one pass per element of n
  assign led = {n[3], n[2], n[1], n[0]};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {4'(sw[15:12] + 3), 4'(sw[11:8] + 2), 4'(sw[7:4] + 1), sw[3:0]})) begin $display("FAIL: foreach, nibble + index (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: streaming concatenation: {<<{sw[7:0]}} (bit reverse) and {<<4{sw[15:8]}}
next: do ... while in always_comb, twice: a popcount, and a loop whose condition is false on entry (its body still runs once, which tells do-while from while)