Install the chain and run your first design. Save your own .sv file anywhere. Open it in VS Code and click ▶ Run on Basys3, or use dewfpga run file.sv from another editor. Standard board pins are automatic; no project folder is needed. Your code determines the circuit.
The full documentation explains the tools, manual setup and hardware limits.
No board and no install? The Basys3 simulator runs your design in the browser, and the testbench runner runs your testbench with a waveform. Not for: Intel Macs, anything from Vivado's IP Catalog, some SystemVerilog that Vivado accepts. Details below.
A recorded blink example from the manual setup
$ make sim
PASS: 3 checks (see the waveform for the toggle)
$ make bit
xdc ok: 33 ports, all mapped.
pnr ok: 73 LUT, 27 FF, 278.71 MHz (PASS at 100.00 MHz) (full log: blink.log)
blink.bit 2.2 MB
$ make flash
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1The blink example on a Basys3, from an M2 with 8 GB. done 1 means the chip accepted the design, and LED 0 starts blinking. 4.6 seconds from .sv to .bit. The chain takes about 0.3 GB of disk (237 MB measured on 7 October; the optional agent SDK adds 51 MB; 1.76 GB if you build it by hand, until you delete what the manual lists); Vivado asks for 50 to 100 GB.
How does it work?
Taking a design from source code to the board involves five jobs. One open-source tool does each job here, plus a chip database generated once, and a small Makefile runs them in order.
| stage | tool |
|---|---|
| simulation | Icarus Verilog |
| synthesis | Yosys |
| place and route | nextpnr-xilinx, built from source |
| bitstream | prjxray fasm2frames + xc7frames2bit |
| chip database | generated once for the XC7A35T |
| programming | openFPGALoader over USB |
Your .sv and .xdc files are the same ones Vivado reads. Use a Basys3 pin file and enable the pins your design uses.
Why does this exist?
Vivado has no macOS build. Setting up the open-source chain by hand took six hours, because of six walls that nobody documents in one place. The setup problems that led to this service. When a step fails, the error text is the fastest way in: every error hit during this setup, with the fix.
What can it not do?
- Nothing from Vivado's IP Catalog: no Block Design, MicroBlaze, AXI, Clocking Wizard or the BRAM, VGA and UART cores. Write your own synthesizable logic for the functions you need; importing a vendor IP block is a separate capability.
- On the Mac chain there is no waveform viewer, schematic or in-chip debugger:
dewfpga simwrites a.vcdfile and stops there. The testbench runner in the browser draws the waveform instead. - Some SystemVerilog that Vivado compiles is refused here, and some builds a wrong bitstream with no error. The constructs measured so far, next to what Vivado does: the list.
- Only the Basys3 (XC7A35T), only Apple Silicon. Intel Macs, Linux and other boards are untested.
- The tools are unofficial. AMD does not make or support them. The limits, in detail.
What is coming?
Available now: the Basys3 simulator, the testbench runner and the command-line tool. Still in progress: compiling a Basys3 bitstream entirely in the browser. Use the command-line tool to build and program the real board.
Who made this?
Damla Su Bilge, Bilkent CS. Everything here was run on 19 and 20 September 2026 on an M2 with 8 GB of RAM, macOS 15 and a Basys3. If a step fails for you, open an issue or write on LinkedIn with the last ten lines of the terminal and the step number.