the guide · 8How do you run CS223 labs on a Mac without Vivado?

What can it not do?

This covers the part of Vivado that CS223 uses, not all of it yet, and nothing beyond it.

• Nothing from Vivado's IP Catalog. No Block Design, MicroBlaze, AXI, Clocking Wizard, or the BRAM, VGA and UART cores. 35 old student repos with 240 source files were searched for those; none use any of it. (Searched, not synthesized.)
• No GUI. No waveform viewer, schematic or in-chip debugger. sim writes a .vcd; the browser testbench draws the waveform for the same files.
• SystemVerilog that Vivado compiles and this chain does not, yet. test/sv in the repository holds one probe for each construct measured so far, each run through sim, bit and a simulation of the synthesized netlist, next to what Vivado does and the source for it (expect.tsv). It is not every construct: each round of testing has found more. On 26 September, 82 of the 111 constructs Vivado supports failed a stage: 58 stop before a bitstream (Yosys refuses them, or the CLI, place and route or its timing check does), 12 fail only in sim (Icarus 13 refuses them or has no model), 2 (an MMCM, and a memory marked as a block RAM) build but have no model to check them against, and 10 build a bitstream that does not do what the code says, with no error: a hierarchical name such as u_fsm.state, $isunknown, the members of an interface used from the module that instantiates it (bus.a, with or without ports, or in an array of interfaces: 3 probes), a package in its own file, reading an inout pin the design sets to a constant z, a design module that calls $finish, a packed 2-D localparam whose type is a typedef (the table comes out as zeros), and two modules nothing instantiates where one is named like its own file (the CLI builds that one, not the top your project names).
• Two parsers. Icarus reads your code for simulation, Yosys for synthesis, and they do not support the same SystemVerilog. Code that passes sim can fail in bit; section 7 lists what the course's files and old student repos hit, and expect.tsv above every construct measured.
• The timing number is nextpnr's estimate. Vivado's report is the official one. In the two designs above the margin was 1.5x (four modules) and 2.8x (blink) over 100 MHz.
• Unofficial tools. AMD does not make or support them; prjxray worked out the bitstream format without AMD's documentation. If a lab is graded in Vivado, open it in Vivado once before the demo.
• Memories become distributed RAM (-nobram). The 16x8 RAM in section 7 mapped to four RAM32M cells. A large memory such as a VGA framebuffer would not fit this way; big multipliers and DSP blocks are untested. The one exception is a memory the code asks to be a block RAM, (* ram_style = "block" *) or (* rom_style = "block" *): Yosys builds a RAMB18E1 then, which the timing check does not time and the test suite cannot simulate (97_ram_style_block).
• One board, one platform. Basys3 (XC7A35T), Apple Silicon. Intel Mac, Linux and other boards are untested and the installer refuses them.
• Confirmed on the board (19 and 20 September): five designs: blink, switches to LEDs, the Lab 2 adder/subtractor, the button counter on the display and the traffic-light FSM with sensor hold (the last three are the simulator's examples). The four-module design in section 7 went as far as a bitstream and was not loaded.
• `ifdef SIM. The browser simulator defines SIM; the command line does not. A design can use it to shorten a clock divider for the browser and keep the real value for the board, as blink.sv does.

previous: 7.1 Which course file breaks?
This section in the whole guide
Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage

Stuck on an error? Every error from this setup, filed under the exact line it printed.