write systemverilog, press run
write your own code, or open folder to load your .sv/.v files and .xdc pin file. click run on board, then try the virtual switches and buttons. edit and run again to see your changes. testbench runs your testbench and draws its waveform. download your files as a zip to build with the CLI. nothing to install; your code stays in this browser.
large counter: simulation timing
For a divider, use a smaller limit under `ifdef SIM. Keep the hardware value in `else; hardware validation reads that branch too. This changes simulated timing, not the FPGA clock.
click a switch to flip it, hold a button to press it. with the board focused, arrows and enter are the five buttons.
hover the waveform for values, wheel to zoom, drag to pan, double-click to reset.