Which error did you get?

3.1oss-cad-suite has no nextpnr-xilinx

the obvious first try, 497 MB later. YosysHQ's bundle ships nextpnr for ice40, ecp5, nexus and Gowin. Not Xilinx.

3.2error: externally-managed-environment

pip, with Homebrew's Python on macOS. PEP 668. Homebrew's Python refuses a plain pip install. The chain needs a venv.

3.3clang++: error: unsupported option '-fopenmp'

nextpnr-xilinx, while compiling on macOS. nextpnr's default build asks Apple's clang for OpenMP, which it does not have.

3.4nextpnr-xilinx: where is the chip database for the XC7A35T?

nextpnr-xilinx, the first time you run it. There is no prebuilt chipdb. It is generated per device from the prjxray data.

3.5Cannot specify include directories for target "yaml-cpp" which is not built by this project

CMake, while configuring prjxray. prjxray was cloned without --recursive, so its submodules are empty.

3.5Compatibility with CMake < 3.5 has been removed from CMake

CMake 4, while configuring prjxray. prjxray is written for an older CMake. CMake 4 refuses it without a policy flag.

4Makefile:29: *** missing separator. Stop.

make, on a Makefile copied from a PDF or a web page. The recipe lines lost their Tab characters when you copied them.

5blink.xdc:42: ERROR [no-iostandard-property]: led[15] has a PACKAGE_PIN but no IOSTANDARD in the XDC: every pin needs both, and nextpnr stops without one. Fix: add the line set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]

dewfpga bit, the XDC check before place and route (nextpnr alone prints the raw form below). A port in your design has no pin in the .xdc file. nextpnr names the wrong port.

7design.sv:3: note [port-neither-input-nor-output]: wrote the port direction in: output logic dp, (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both)

dewfpga bit, the source scan before the tools run (Yosys alone prints the raw form below). The course's seven-segment module has a broken port line. Vivado accepts it, Yosys does not.

flashERROR [board-not-found]: board not found by openFPGALoader: it could not open the Basys3 USB interface. Fix: check power and the PROG data cable; if macOS lists the Digilent device, check whether this process can access USB. A failed open does not prove the board is unplugged.

openFPGALoader, when you program the board. The programmer could not open the Basys3 USB interface. Check physical connection and, if macOS sees the device, the programming process's USB access.

checkERROR [unknown-command]: unknown command: nope. Fix: one of the commands below.

dewfpga, before anything runs. The word after dewfpga is not one of its commands (install, check, new, sim, bit, flash, clean, uninstall).

checkERROR [unknown-option]: unknown option: --x; dewfpga bit takes a module or a file name, nothing else. Fix: dewfpga bit [top] (dewfpga --help lists the commands).

dewfpga bit / sim / flash / install, before anything runs. A word starting with - after the command, or an argument after install: the commands take a module or file name at most, install takes nothing.

bitERROR [no-source-file]: no .sv or .v file in /Users/you/lab4. Fix: cd into the folder with your design, or start one: dewfpga new blink

dewfpga sim / bit, before anything runs. The current folder holds no .sv or .v file; dewfpga works on the files in the folder you run it in.

bitERROR [run-inside-the-folder]: w/blink is a path, and dewfpga works on the .sv files in the current folder. Fix: run it inside the folder that holds the .sv files: cd "w" && dewfpga bit blink

dewfpga sim / bit, before anything runs. The argument holds a slash: the CLI takes a module or a file name in the current folder, not a path.

bitERROR [file-name-with-space]: 'my blink.sv': file names with spaces are not supported by the tools. Fix: rename it (e.g. my_blink.sv).

dewfpga sim / bit, before anything runs. A .sv, .v or .xdc file name with a space in it; yosys, iverilog and nextpnr take file lists split at spaces.

checkERROR [path-with-space]: a path with a space (/Users/you/My Projects/dewfpga / /Users/you/fpga): the FPGA tools cannot handle that. Fix: move the folder to a path without spaces, or set FPGA_HOME to one.

dewfpga, before anything runs. The CLI's own folder or FPGA_HOME has a space in its path; the build scripts hand those paths to make and the tools unquoted.

bitblink.sv:1: ERROR [utf8-bom]: blink.sv starts with a byte-order mark (saved as 'UTF-8 with BOM'), and yosys stops at its first token. Fix: save it as plain UTF-8, or remove it: LC_ALL=C sed -i '' $'1s/^\xEF\xBB\xBF//' blink.sv

dewfpga sim / bit, before anything runs. The file starts with the three invisible bytes EF BB BF that Notepad and some editors write; yosys reads them as a token it does not know.

checkERROR [folder-exists]: w already exists, and dewfpga new does not overwrite. Fix: pick another name, or cd w and work there.

dewfpga new. The folder dewfpga new was told to create is already there; it never overwrites a design.

bitERROR [no-xdc-file]: no .xdc pin file in this folder, and these ports of adder have no board name: a b y. Ports named like the board's (clk sw led btnC btnU btnD btnL btnR seg dp an) need no .xdc. Fix: rename those ports, or copy ~/.dewfpga/templates/Basys3_Master.xdc here and uncomment the pins you use.

dewfpga bit / flash, before synthesis. The folder has no .xdc and some ports have names the board does not use, so nothing says which pin they go to; ports with the board's names get their pins without a file.

bitERROR [two-xdc-files]: 2 .xdc files here (a.xdc b.xdc) and none is named blink.xdc, so nothing says which one holds the pins. Fix: keep one, or name it blink.xdc.

dewfpga bit / flash, before synthesis. Several .xdc files in the folder and none named after the top module; the CLI does not guess which one is the pin file.

simERROR [no-testbench]: no testbench for blink in this folder: a testbench is a module without ports that instantiates blink and ends with $finish; blink_tb.sv is the usual name. Fix: write one next to the design; 'dewfpga new blink' gives an example (blink/blink_tb.sv).

dewfpga sim, before iverilog. No module without ports instantiates the top module, so there is nothing to simulate it with.

bitERROR [no-top-module]: could not find a top module in blink.sv blink_tb.sv. Fix: name it: dewfpga bit <module>

dewfpga sim / bit, before anything runs. The source scan ended without a top module and without a reason; naming the module on the command line settles it.

checkERROR [toolchain-not-installed]: something is missing (the ✗ rows above), so dewfpga bit and flash cannot run. Fix: dewfpga install (safe to re-run; it only builds what is missing).

dewfpga check, or dewfpga bit / flash before synthesis. nextpnr-xilinx, the chip database or another tool is not under FPGA_HOME; the build needs all of them.

checkERROR [yosys-slang-does-not-load]: /Users/you/fpga/yosys-slang/build/slang.so was built for another yosys (brew upgrade yosys leaves it behind), so the SystemVerilog yosys' own reader refuses would not build. Fix: dewfpga install (it rebuilds the reader, about 4 min).

dewfpga check. The second reader is a plugin compiled against one yosys; after brew upgrade yosys it no longer loads.

checkERROR [fpga-home-unsafe]: FPGA_HOME is /Users/you; refusing to delete that. Fix: remove the six entries by hand: nextpnr-xilinx yosys-slang prjxray chipdb venv install.log

dewfpga uninstall. FPGA_HOME points at your home folder or /; uninstall deletes what install.sh put under FPGA_HOME and will not touch those.

checknote [no-install-found]: nothing to remove: no dewfpga install found in /Users/you/fpga (FPGA_HOME=/elsewhere dewfpga uninstall for one installed elsewhere).

dewfpga uninstall. Not an error: uninstall found none of the six entries install.sh writes under FPGA_HOME.

bitSevSeg_4digit.sv:42: note [explicit-port]: wrote the port as a plain name: a, b, c, d, e, f, g, dp,

dewfpga run / sim / bit, the source preparation before the tools run. Not an error: a port list in Vivado's netlist form names a port with an expression, .dp(\<const0> ), which Vivado builds and yosys' reader does not; the copy the tools read writes it as a plain port.

bitlab1_top.sv:27: ERROR [module-without-endmodule]: module lab1_top (lab1_top.sv:21) has no endmodule: line 27 reads endmodulek. Fix: write endmodule on line 27.

dewfpga run / sim / bit, the source scan before the tools run. A module's endmodule is missing or misspelled, so the module never ends; the scan stops here instead of naming the wrong top.

bitcounter.sv:4: ERROR [two-tops]: 2 modules could be the top (nothing instantiates them): counter (counter.sv:4), top (counter.sv:8). Fix: name it: dewfpga bit counter

dewfpga sim / bit, the source scan before the tools run. Two or more design modules that nothing instantiates; the CLI does not pick one by file name (Lab 4 folders name the file after the wrong one).

bitblink_tb.sv:6: ERROR [top-is-a-testbench]: blink_tb is a testbench (it has no ports), not a design. Fix: name a design module instead: dewfpga bit blink.

dewfpga sim / bit, the source scan before the tools run. The module named on the command line has no ports, so it is a testbench; a bitstream needs a design with ports.

bitERROR [no-such-module]: no module named nope in blink.sv blink_tb.sv; the modules here: blink. Fix: name one of them, or the file that holds it: dewfpga bit blink

dewfpga sim / bit, the source scan before the tools run. The name on the command line is neither a module nor a file of this folder.

bitERROR [no-design-module]: no design module in blink_tb.sv (only testbenches). Fix: a design is a module with ports; put it in a .sv file in this folder, or start one: dewfpga new blink

dewfpga sim / bit, the source scan before the tools run. Every module in the folder has no ports; there is nothing to build.

bitdesign.sv:1: ERROR [module-defined-twice]: module top is defined twice: design.sv:1 and design_old.sv:2; the last one read would win silently. Fix: keep one, or move the backup out of this folder.

dewfpga sim / bit, the source scan before the tools run. Two files in the folder declare the same module; the tools would take the last one read, so a backup could be built instead of the design.

bitdesign.sv:6: ERROR [finish-in-design]: $finish in a design module (top): Vivado ignores it (UG901 Table 21: $finish Ignored) and yosys stops on it. Fix: remove it, move the check to the testbench, or wrap it in `ifndef SYNTHESIS ... `endif.

dewfpga sim / bit, the source scan before the tools run. A $finish or $stop inside a module with ports; there is no hardware for it, and yosys stops on it where Vivado drops it.

bitdesign.sv:2: ERROR [decl-init-reads-signal]: `sum = sw[3:0] + sw[7:4]` in a declaration is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8; yosys makes it the power-up value, so the board never follows sw). Fix: write assign sum = sw[3:0] + sw[7:4]; and declare sum without the = part.

dewfpga sim / bit, the source scan before the tools run. `logic [3:0] sum = sw[3:0] + sw[7:4];` sets a power-up value from a signal; it is not a continuous assignment, and the board would show the value from time 0 forever.

bitdesign.sv:5: note [unnamed-instance]: named the instance: inv u_inv(sw[0], led[0]); (in the copy the tools read, your file stays as you wrote it; the standard and Yosys need it; Vivado accepts both)

dewfpga sim / bit, the source scan before the tools run. `inv(sw[0], led[0]);`, an instance without a name: Vivado accepts it, the standard and yosys do not, so the CLI names it u_inv in a temporary compiler copy and says so. Your saved source stays unchanged.

bitleftover_func_synth.v:2: ERROR [vivado-netlist-in-folder]: leftover_func_synth.v is a netlist Vivado wrote after synthesis, not source code (its header says so, and Yosys cannot read it); Vivado writes these under .sim/ and .runs/. Fix: delete it from this folder and keep your own .sv files.

dewfpga sim / bit, the source scan before the tools run. A .v file whose header says it is a Vivado post-synthesis simulation netlist sits next to the sources; it is not a design and yosys cannot read it.

bitblink.xdc:42: ERROR [port-without-pin]: led[15] has no pin in the XDC: the line that names it starts with # (commented out), so it does not count. Fix: remove the # at the start of that line (the same name, the index the design uses: led[15]).

dewfpga bit, the XDC check before place and route. A port of the top module has no PACKAGE_PIN line in the XDC: the line is commented out, the index is missing, the name differs.

bitblink.xdc:5: ERROR [no-such-pin]: ZZ99 is not an I/O pin of the Basys3's chip (xc7a35tcpg236; a pin is a letter and a number, in capitals: W5, U16, V17), so clk would have no pin and nextpnr would stop here. Fix: write the pin clk is wired to on this line (the course's Basys3_Master.xdc puts clk on W5): copy its line from Basys3_Master.xdc, or take the pin from the board's schematic.

dewfpga bit, the XDC check before place and route (nextpnr alone prints the raw line below, with no file:line). A PACKAGE_PIN in the XDC names a pin the chip does not have: a typo, a pin of another board, a power pin, or a pin written in small letters (w5).

bitblink.xdc:27: ERROR [pin-used-twice]: pin U16 is given to 2 ports, clk (blink.xdc:5) and led[0] (blink.xdc:27): one pin takes one port, so nextpnr would stop here. Fix: give each port its own pin: copy their lines from the course's Basys3_Master.xdc (clk is on W5, led[0] is on U16).

dewfpga bit, the XDC check before place and route (nextpnr alone prints the raw lines below). Two ports of the design have the same PACKAGE_PIN in the XDC: a copied line whose pin was not changed.

bitblink.xdc:43: warning [xdc-get-ports-form]: `get_ports {led[*]}` is a wildcard: Vivado expands it, and this check does not read that form yet, so the ports it names count as unpinned here. Fix: write one line per port with its full name, as the course's Basys3_Master.xdc does: set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]

dewfpga bit, the XDC check before place and route. A get_ports with a wildcard, a list of several ports or an option (-regexp, -filter): Vivado expands those, this check reads one full port name per line.

bitblink.xdc:43: warning [xdc-port-case]: the XDC names 'LED[3]' but the design's port is spelled led (same name, different case), so this line is an unused pin. Fix: make the two spellings the same.

dewfpga bit, the XDC check before place and route. An XDC line names a port that differs from the design's only in case; names are case-sensitive, so the line pins nothing.

simdesign.sv:4: ERROR [iverilog-refused]: iverilog cannot compile this code (its message is above). Fix: fix the first line it names; the errors after the first often follow from it.

dewfpga sim, iverilog. iverilog stopped with an error; its own lines are above, and this line names the first of them.

simdesign.sv:3: note [sim-from-build]: iverilog cannot compile this design (its lines are above), so the simulation runs on the design as the build reads it: read by yosys' own reader, written back as Verilog (top_sim.elab) and compiled with the testbench and yosys' models of the Xilinx cells. What differs: a # delay in the design is gone, an `ifdef SYNTHESIS branch is taken, and a signal the testbench reaches by its hierarchical name (dut.state) may be renamed or gone.

dewfpga sim, after iverilog refused a line of the design. Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

simtop_tb.sv:3: ERROR [sim-from-build-parameters]: iverilog cannot compile the design (its lines are above), and the testbench sets parameters of top with #(...): the simulation of the design as the build reads it keeps top's parameters at their defaults, as the bitstream does, so the testbench's values would not apply and its checks would test another design. Fix: rewrite the line iverilog names above so that iverilog compiles the design itself (the page lists what to write instead of each construct), or test top with its defaults (no #(...) in the testbench).

dewfpga sim, after iverilog refused a line of the design. iverilog refused the design and the testbench sets the top module's parameters; the simulation of the design as the build reads it cannot apply them, so it stops instead of testing another design.

simnote [sim-starts-as-board]: 3 registers without a start value start as the board does, not at x: a at 4'b0101 and b at 4'b1010 (their reset values), c at 0 (no reset). Vivado's simulator shows x there until the first reset; a start value in the declaration (logic [3:0] c = 0;) is honoured by every tool (UG901 v2022.2 Ch.4 p.79).

dewfpga sim, after iverilog compiled the design. Not an error: a register or a memory of the design has no start value, and the simulation starts it where the board starts it (the reset value; 0 without a reset; a LUT RAM word at 0) instead of x, so a case or an if that reads it before the first reset takes the same branch in the simulation and on the board.

simERROR [sim-timeout]: the simulation did not finish in 120 s: the testbench never reached $finish (a free-running clock never stops on its own). Fix: end the testbench with $finish; SIM_TIMEOUT=600 dewfpga sim waits longer.

dewfpga sim, vvp. The testbench never called $finish, or needs longer than the timeout; the CLI killed the simulator.

simERROR [sim-exit]: the simulator stopped with exit 1 (its message is above: a $fatal, or a testbench that ends without $finish). Fix: read the line above this one and fix what it names; make the testbench end with $finish.

dewfpga sim, vvp. vvp ended with a non-zero exit: a $fatal in the testbench, or a run that ended without $finish.

simblink_tb.sv:17: ERROR [testbench-error]: the testbench reported 2 errors (its ERROR: lines above, from $error): the design does not do what the testbench expects. Fix: read the first ERROR: line, it names the check that failed; fix the design there, or the testbench if its expectation is wrong.

dewfpga sim, after vvp. The simulation ran to $finish, and the testbench printed ERROR: lines with $error: a check failed.

bitdesign.sv:4: ERROR [packed-typedef-2d]: SEG is declared with the type tab_t, a packed array with two dimensions (design.sv:3): yosys keeps a value of such a typedef as one flat vector, so SEG[i] picks one bit instead of one row, and the table would be built wrong. Fix: write the dimensions on the declaration itself: logic [3:0][6:0] SEG; a parameter yosys refuses in that form, so keep it flat and take a row with +: (localparam logic [N*W-1:0] SEG = {...}; SEG[i*W +: W]).

dewfpga sim / bit, the typedef scan before the tools run. A typedef of a two-dimensional packed array used to declare a parameter or a net; yosys flattens the type and every row index picks one bit.

bitdesign.sv:2: ERROR [ref-argument]: function inc takes an argument by reference (ref logic [3:0] x): yosys does not read ref, and yosys-slang drops it, so the variable it is called with would never change on the board. Fix: pass the value in and return it (function automatic logic [3:0] inc(input logic [3:0] x); ... return x + 1; and v = inc(v);).

dewfpga bit, the source scan before the tools run. A function or task argument passed by reference; yosys' reader stops on it and yosys-slang builds the call as nothing.

bitdesign.sv:2: ERROR [package-file-not-given]: cfg_pkg::MAGIC names the package cfg_pkg, which is declared in pkg.svh, and the tools are not given that file (they read what dewfpga collected, every .sv and .v of the folder or of the project: design.sv; a .svh or .vh reaches them only through an `include, a file outside the folder or the project not at all): iverilog stops at a syntax error there; yosys would drop the import and build every name of cfg_pkg as an undriven 1-bit wire: x on the board. Fix: add `include "pkg.svh" as the first line of design.sv; or move the package into design.sv, above the module.

dewfpga sim / bit, the source scan before the tools run (or yosys). The package lives in a file the tools are not given: a .svh or .vh that no design file `includes, or a file outside the folder or the project.

simtb.sv:1: ERROR [included-twice]: tb.sv `includes pkg.sv, and the simulator reads pkg.sv with the design already (dewfpga hands every .sv and .v of the folder to the simulator, a package file first: pkg.sv design.sv): read a second time, package cfg_pkg is declared twice and iverilog stops at its first line ('syntax error', 'I give up'). Fix: delete the `include "pkg.sv" line from tb.sv; cfg_pkg reaches the testbench through the design, which iverilog reads first.

dewfpga sim, the source scan before iverilog runs. The testbench `includes a file the simulation reads with the design already (a package file of the folder, or one the design `includes), so the package is declared twice and iverilog stops.

bitdesign.sv:2: ERROR [package-not-found]: `import cfg_pkg::*` names the package cfg_pkg, and no file in this folder declares it (package cfg_pkg; ... endpackage). Fix: check the spelling, or add the file that declares it and `include it as the first line of design.sv.

dewfpga sim / bit, the source scan before the tools run. An import or pkg::NAME names a package no file in the folder declares.

bitdesign.sv:2: ERROR [isunknown-in-design]: $isunknown in a design: on the board a signal is never x, so it is 0 there (and dewfpga sim shows 0); yosys folds it to the constant 1 instead, so the bitstream would not do what the simulation showed. Fix: remove it from the design; $isunknown belongs in the testbench.

dewfpga bit, the source scan before yosys. $isunknown in synthesizable code; a chip has no x, and yosys folds the call to a constant that differs from the simulation.

bitdesign.sv:3: warning [latch]: latch inferred for q (an if without else in always_comb): q keeps its value when no branch assigns it; Vivado builds the latch too, with the same warning (UG901 Ch.5 Latches). Fix: if you meant a register, write always_ff with a clock; if a latch, always_latch; if neither, give q a value on every path (an else branch, or a default at the top of the block).

dewfpga bit, yosys. A combinational block leaves a signal unassigned on some path, so it has to remember its value: a latch, built as Vivado builds it, with the same warning.

bitdesign.sv:3: ERROR [latch-loop]: latch inferred for q (an if without else in always_comb), and yosys built it as a LUT feedback loop, not a latch, so the board would not do what the simulation showed; Vivado builds an LDCE latch here, with a warning (UG901 Ch.5 Latches). Fix: give q a value on every path (an else branch, or a default at the top of the block); if you meant a latch, write always_latch instead of always_comb (both readers build that as a latch).

dewfpga bit, yosys. A latch the reader turned into a combinational loop instead of a latch cell; the loop does not behave like the simulation, so the build stops.

sim, bitdesign.sv:5: ERROR [unique-case-overlap]: the items 4'b10?? (design.sv:4) and 4'b??11 (design.sv:5) of this unique casez both match 4'b1011, and unique promises that only one item can match: the simulation takes the first item (iverilog ignores unique), and the hardware, built as parallel logic the way Vivado builds a unique case (UG901 Ch.10, parallel_case), ORs the two items' values, so the board would not do what the simulation showed. Fix: make the items disjoint (4'b10?? and 4'b0?11), write priority casez when the first match should win, or drop unique.

dewfpga sim and dewfpga bit, the source scan before the tools. Two items of a unique casez (or casex) can match the same value; the simulator takes the first, the hardware ORs both, so the board would not do what the simulation showed.

bitdesign.sv:4: warning [latch-hazard]: always_latch builds a latch for led (an LDCE cell, as Vivado builds it, UG901 Ch.5 Latches), and a latch has no clock: when its gate (s < sw) closes in the same instant its data changes, the board keeps the old value or takes the new one depending on which wire is faster, where the simulation always keeps the old one; dewfpga sim cannot show that race. Fix: if a register was meant, write always_ff @(posedge clk) with the gate as its enable: if (s < sw) led <= ...; keep always_latch only when the gate is held steady while the data changes.

dewfpga bit, yosys. An always_latch whose gate and data come from the same inputs: when both change at once the board races, where the simulation keeps the old value; the build goes on with the warning.

sim, bitdesign.sv:7: ERROR [implicit-port-width]: the .* connection of u (module sub) joins the port sub_out, 8 bits wide with N = 8, to the signal sub_out declared 4 bits wide: an implicit connection (.* or .sub_out) takes the port and the signal exactly as declared, with no padding or cutting (IEEE 1800-2017 23.3.2.3), so neither reader builds it, where dewfpga sim (iverilog) widened the signal to the port, so the port's 4 high bits reach nothing (its line: Padding 4 high bits of the port) and ran. Fix: declare sub_out with the port's width (logic [7:0] sub_out;), or connect it by name, .sub_out(sub_out), which pads or cuts to the port's width as the simulation did.

dewfpga sim and dewfpga bit, yosys (or yosys-slang). A .* or .name port connection whose port and signal widths differ: the simulator pads or cuts and runs, neither synthesis reader builds it; the same line at sim and at bit names the port, the two widths and the fix.

bitdesign.sv:3: ERROR [async-reset-nonconst]: this always_ff has an asynchronous reset (posedge clk or posedge btnC), so on btnC's edge every signal it writes must get a constant; here q is loaded from sw. yosys emulates that with FFs and a mux, so the board would not do what the simulation showed. Fix: reset to a constant, and load sw with the clock, behind an input of your own (load): if (btnC) q <= 0; else if (load) q <= sw; else q <= q + 1;

dewfpga bit, yosys. In an always_ff with an asynchronous reset, the reset branch loads a register from a signal, or a signal is written outside the reset if/else; a flip-flop can only reset to a constant.

bitdesign.sv:3: ERROR [async-reset-polarity]: this always_ff is sensitive to posedge btnC, but its first if tests !btnC, so the reset branch runs while btnC is low and on btnC's rising edge the block takes the else branch, which loads q from sw: no flip-flop on the chip loads a signal on its reset edge (yosys emulates it with FFs and a mux, so the board would not do what the simulation showed). Fix: test btnC at the level its edge leaves it: if (btnC) q <= 0; else ...; or keep if (!btnC) and write negedge btnC in the sensitivity list.

dewfpga bit, yosys. The sensitivity list names one edge of the reset and the first if tests the other level, so the reset edge lands in the else branch, which loads a signal.

bitdesign.sv:3: ERROR [async-reset-not-alone]: this always block is sensitive to two edges (@(posedge clk, posedge btnC)), so one of them is an asynchronous reset, but its first if does not test that reset alone (a reset ORed with a synchronous clear: if (rst || clear)), so neither reader can tell the reset from the clock. Fix: test the reset alone first and put the synchronous clear in the else: if (btnC) q <= 0; else if (clear) q <= 0; else q <= q + 1;

dewfpga bit, yosys. The block has a clock and an asynchronous reset in its sensitivity list, but the first if tests the reset ORed with another signal.

bitdesign.sv:3: ERROR [dual-edge]: this always block is sensitive to both edges of clk (@(posedge clk or negedge clk)), so cnt would change on every edge: no flip-flop on the chip does that, and neither reader builds it. Fix: clock the block on one edge (always_ff @(posedge clk)); for twice the rate use a faster clock (the Basys3's is 100 MHz) or count on both phases with two registers.

dewfpga bit, yosys. One always block clocked on posedge and negedge of the same clock; the chip's flip-flops have one clock edge.

bitdesign.sv:3: ERROR [initial-from-signal]: `num = sw` here is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8), and the chip has no power-up value that follows a signal, so yosys stops. Fix: for a wire write assign num = sw; for a register give num a constant start value (logic [15:0] num = '0;) and load sw with the clock (if (btnC) num <= sw;).

dewfpga bit, yosys. An initial block, or a declaration, sets a register's start value from a signal; power-up values are constants.

bitdesign.sv:3 and design.sv:4: ERROR [two-always-drivers]: cnt is written from two always blocks (design.sv:3 and design.sv:4): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive cnt from one always block (merge the two, or give each block its own signal).

dewfpga bit, yosys. The same register is assigned in two always blocks; yosys resolves the conflict silently, Vivado refuses it.

bitdesign.sv:4 and design.sv:6: ERROR [always-and-assign]: q is written by an always block (design.sv:4) and by a continuous assign (design.sv:6): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive q from one of them.

dewfpga bit, yosys. A signal assigned both in an always block and with assign; two drivers on one wire.

bitdesign.sv:2 and design.sv:3: ERROR [two-assign-drivers]: led is written by two continuous assigns (design.sv:2 and design.sv:3): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive led from one assign (select with a mux: assign led = sel ? b : a;).

dewfpga bit, yosys. A signal with two assign lines; two drivers on one wire.

bitdesign.sv:3 and design.sv:7: ERROR [multiple-drivers]: q is written from more than one place (design.sv:3 and design.sv:7): yosys resolved the conflict to a constant, so the board would not do what the simulation showed. Fix: drive q from one always block or one assign; give each other writer its own signal.

dewfpga bit, yosys. A signal written from more than one place that the checker could not sort into always blocks and assigns; two drivers on one wire.

bitdesign.sv:4: ERROR [undeclared-name]: summ is not declared anywhere and nothing drives it: yosys made it a 1-bit wire stuck at x and built the design without it (dewfpga sim refuses this code). Fix: declare it, or check the spelling (a typo of a declared name).

dewfpga bit, yosys. A name used but never declared; yosys' reader makes an implicit 1-bit wire with no driver, so the design would be built without it.

bitdesign.sv:7: ERROR [hierarchical-name]: u_cnt.count is a hierarchical name (a signal inside another instance). yosys does not resolve it (it made a 1-bit wire with no driver, so the board would not do what the simulation showed); Vivado resolves hierarchical names (UG901 Ch.9 Table 20). Fix: bring that signal out through an output port of its module and connect it here.

dewfpga bit, yosys (when yosys-slang is not installed). A signal reached through an instance name (u_cnt.count); yosys' own reader does not resolve it. With yosys-slang installed the design builds, with the read-with-slang note.

bitdesign.sv:9: ERROR [interface-member]: bus.data is a member of the interface instance bus, used in the module that instantiates it. yosys does not resolve it (it made a 1-bit wire with no driver, so the board would not do what the simulation showed); an interface used this way is not supported yet (#4). Fix: pass the interface to a module through an interface port, or keep those signals as plain logic in the module.

dewfpga bit, yosys (when yosys-slang is not installed). A member of an interface instance read in the module that declares the instance; yosys' own reader makes an undriven wire of it. With yosys-slang installed the design builds.

bitdesign.sv:5: ERROR [module-not-found]: the module counter is instantiated here, and no file the build was given declares it (dewfpga reads the files that hold a module: design.sv). Fix: put the file that declares counter in this folder, or check the spelling of the module name.

dewfpga bit, yosys. An instance of a module no file in the folder declares.

bitdesign.sv:5: ERROR [enum-method-next-prev]: s.next() is an enum method that steps through the values (next/prev): yosys does not build enum methods, and yosys-slang builds first()/last() only; Vivado builds next/prev (UG901 Ch.10 Table 27). Fix: write the step out as a case on s, in the order the enum lists its values (with IDLE, RUN, DONE: case (s) IDLE: s <= RUN; RUN: s <= DONE; DONE: s <= IDLE; endcase).

dewfpga bit, yosys-slang. The enum methods next() and prev(); neither reader builds them, Vivado does.

bitblink.v:8: ERROR [slang-refused]: use of undeclared identifier 'logic' (yosys-slang, the second reader; yosys' own reader refused this code too, its line is above). Fix: the caret below marks the construct; the page lists the usual ones and what to write instead.

dewfpga bit, yosys-slang, after yosys' own reader refused the code. Both readers refused the code; yosys' own line is printed first, then yosys-slang's error with its caret.

bitERROR [slang-unimplemented]: yosys-slang cannot build a construct of this design yet (ERROR: Feature unimplemented at slang_frontend.cc:776, see AST and code line dump above), and yosys' own reader refused the code too (its line is above). Fix: take the design apart until the build goes through, and report that construct (github.com/nosey-dewdrop/dewfpga/issues).

dewfpga bit, yosys-slang, after yosys' own reader refused the code. yosys-slang stops on a construct it has no implementation for, without a line; the code line dump above it shows the construct.

bitdesign.sv:2: ERROR [yosys-crashed]: yosys' own reader crashed (Segmentation fault: 11) without a message, and this line holds a real number (1e1): a real value in a parameter (localparam MAX = 1e1) is a known cause. Fix: write the value as an integer (10, 50_000_000).

dewfpga bit, yosys. yosys died with a signal instead of an error message; a real literal in a parameter is the known cause, and the line that holds one is named.

bitnote [second-reader-missing]: yosys' own reader refused this code, and yosys-slang, the second reader (it reads the SystemVerilog Vivado accepts: interfaces, unpacked arrays, foreach, break, enum methods first/last ...), is not installed: /Users/you/fpga/yosys-slang/build/slang.so not found. Fix: run dewfpga install (it builds that reader, ~3 min), then build again.

dewfpga bit, after yosys' own reader refused the code. The code needs the second reader, and it is not built; the error above it may go away with it.

bitnote [read-with-slang]: top read with yosys-slang, the second reader (yosys' own reader refused this code; the build is the same from here).

dewfpga bit, synthesis. Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

bitnote [v-is-verilog-2005]: a .v file is read as Verilog-2005 by both readers, as Vivado reads it (UG901 Ch.10): SystemVerilog (logic, always_ff, always_comb, enum ...) belongs in a .sv file. Fix: if your .v file holds SystemVerilog, rename it to .sv.

dewfpga bit, after both readers refused a .v file. A .v file that holds SystemVerilog; both readers, like Vivado, read .v as Verilog-2005, so logic and always_ff are syntax errors there.

bitdesign.sv:3: note [fsm-encoding-kept]: (* fsm_encoding = "one_hot" *) on state is not applied: the netlist keeps the 2-bit codes the declaration gives state, so its power-up (every flip-flop at 0, as the board starts a register without a start value) is the state with code 0, the one dewfpga sim starts in; re-encoded, the flip-flops would start in no state until the first reset (the netlist and the board would sit dark where the simulation moved on). Vivado applies the attribute (UG901 FSM_ENCODING), and the guide does not say what its re-encoded register holds before the first reset. Fix: none needed for this board, and the attribute may stay for Vivado; to start state in a state other than the one with code 0, give it a start value in its declaration (state_t state = RUN;), which every tool honours.

dewfpga bit, synthesis, before yosys reads the design. Not an error: a state register carries an fsm_encoding attribute, and the build keeps the codes the declaration gives it instead of letting yosys re-encode the register, so it powers up in the state with code 0, where dewfpga sim starts it; the build goes on.

bitnote [no-create-clock]: no create_clock in Basys3_Master.xdc; timing is checked against the Basys3's 100 MHz oscillator (--freq 100).

dewfpga bit, before place and route. Not an error: the XDC has no create_clock line, so every clock is checked at the board's 100 MHz.

bitdesign.sv:2: ERROR [internal-tristate]: a tri-state driver (a z, at design.sv:2) on a signal that is not an inout pin of the top module: the chip has tri-state buffers on its pins only. Vivado converts such a driver to logic (UG901 Ch.5 Tristates); yosys keeps it as a $_TBUF_ cell, and nextpnr has nothing to place it on. Not a size problem. Fix: select with a mux instead: assign bus = sel ? b : a; and keep z for an inout pin only.

dewfpga bit, nextpnr. A z driven onto an internal signal or a submodule port; the chip's tri-state buffers sit on pins only, and yosys keeps the buffer as a cell nextpnr cannot place.

bitdesign.sv:3 and design.sv:4: warning [tristate-to-logic]: bus has two tri-state drivers (a z, at design.sv:3 and design.sv:4) and is not an inout pin of the top module: the chip has tri-state buffers on its pins only, so yosys built the two drivers as logic, as Vivado does (UG901 Ch.5 Tristates). On the board bus is never z: with no driver on it shows one driver's value, with both on the other's, where the simulation shows z and x. Fix: select with a mux instead, so the simulation shows what the board does: assign bus = sel ? b : a; and keep z for an inout pin only.

dewfpga bit, yosys. Two z drivers on one internal bus in one module; yosys builds them as logic, as Vivado does, so the board never shows the z or x the simulation shows.

bitdesign.sv:2: ERROR [wired-net]: a wor/wand net (declared at design.sv:2 and design.sv:3) with two drivers: yosys keeps the wired OR/AND as a $and cell, and nextpnr has nothing to place it on. Not a size problem. Fix: write the resolution yourself, in one assign: assign any = sw[3:0] | sw[7:4]; (wand: &), and declare the net as logic.

dewfpga bit, nextpnr. A wor or wand net with several drivers; yosys keeps the wired resolution as a $and/$or cell nextpnr cannot place.

bitdesign.sv:3: ERROR [power-operator]: ** with a base that is a signal (sw ** 2): yosys builds ** only for a constant base and exponent, or 2 ** n, and leaves this one as a $pow cell nextpnr has nothing to place on. Not a size problem. Fix: write the multiplication out (sw * sw), a table (case), or 1 << n for a power of two.

dewfpga bit, nextpnr. The ** operator with a variable base; yosys builds only constant powers and 2 ** n.

bitdesign.sv:2: ERROR [empty-module]: the module blinker (design.sv:2), instantiated as u_blink, has no body (no assign, no always), so yosys kept it as a black box, and nextpnr has no cell of that type to place. Not a size problem. Fix: write the body of blinker, or comment the instance u_blink out until it is written.

dewfpga bit, nextpnr. An instance of a module with ports and no body; yosys keeps it as a black box, nextpnr has no cell of that type.

bitERROR [design-too-big]: the design does not fit the XC7A35T (no SLICE_LUTX left: 20800 LUTs, 41600 FFs; a memory is built from LUTs as distributed RAM, unless (* ram_style = "block" *) asks for a block RAM). The counts are in top.log. Fix: make it smaller: fewer bits, a smaller memory, one divider or multiplier shared over several cycles.

dewfpga bit, nextpnr. nextpnr ran out of a real resource of the chip; the counts are in the log.

bitERROR [timing-not-met]: timing not met: clk 33.61 MHz (FAIL at 100.00 MHz). The longest path between two registers takes more than one period of that clock, so the design cannot run at it, and no bitstream is written; top.log has the critical path report (the registers and the logic between them). Fix: make the path shorter (a divide or a modulo in one cycle is the usual cause: register the intermediate results), or give it the time it needs: create_clock -period 30.000 [get_ports clk] (33.3 MHz) makes the check pass, and the Basys3 pin gives 100 MHz whatever the XDC says (its oscillator, Basys3 reference manual), so those registers must then take a new value only every 3 clocks or more (a clock enable from a counter: if (tick) ...).

dewfpga bit, nextpnr's timing report. The longest path between two registers is longer than the clock period; the CLI writes no bitstream where Vivado would, with a critical warning.

bitERROR [empty-fasm]: top.fasm has no FASM features (an empty or corrupt place-and-route output, usually a build interrupted half way). Fix: run dewfpga clean and build again.

dewfpga bit, after place and route. The place-and-route output file is empty, usually from a build interrupted between nextpnr and the bitstream.

flashERROR [openfpgaloader-failed]: openFPGALoader stopped with exit 1 (its message is above). Fix: read the lines above; a board that answers but refuses the bitstream usually needs the power switched off and on.

openFPGALoader, when you program the board. The board was found, and programming still failed; openFPGALoader's own lines above say why.

project discoveryERROR [two-vivado-projects]

dewfpga, before choosing a project. More than one .xpr file is present, so the CLI cannot choose the intended project.

project discoveryNEW.xpr:11: ERROR [vivado-file-missing]: NEW.xpr lists $PPRDIR/../archive/counter2.sv (../archive/counter2.sv), and that file is not there.

the Vivado project file list. An enabled source or constraint entry names a file that is absent from this checkout.

project discoveryNEW.xpr:1: ERROR [vivado-project-unreadable]

the Vivado XML reader. The project file is not parseable Vivado XML.

project discoveryMIX.xpr:1: ERROR [vivado-path-unknown]

the Vivado source path reader. A listed path uses a Vivado variable that this CLI cannot resolve.

project discoveryMIX.xpr:1: ERROR [vivado-set-ambiguous]

the active Vivado file-set selection. The project does not identify which of several source, constraint or simulation sets to use.

vscodetasks.json:1: ERROR [vscode-tasks-unreadable]

the user-task configuration reader. The task document or its ownership record cannot be interpreted safely.

vscodetasks.json:1: ERROR [vscode-tasks-conflict]

the user-task ownership check. An existing task label or input id collides with the proposed configuration without verified ownership.

vscodetasks.json:1: ERROR [vscode-tasks-write-failed]

the user-task file writer. Writing or replacing the task document or ownership record failed.

vscodenote [vscode-not-found]

the optional editor setup. The VS Code command is unavailable; the FPGA command-line toolchain can still be used.

vscodeERROR [vscode-extension-install-failed]

the companion extension installer. The companion extension could not be built, installed or verified.

vscode removalnote [vscode-linter-shim-retained]

the companion extension ownership check. The companion is retained because a settings value still points to its linter shim, or settings cannot be checked safely.

sim / synthdewfpga could not create its temporary work folder

private Verilog-2005 source wrappers. The build directory is not writable, or the disk has no space for the temporary source copies.

agent CLIThe command exceeded its time limit

JSON command deadline. The JSON wrapper stopped a command that did not finish within its deadline.

agent CLIThe wrapper could not produce a complete command result

JSON output capture. Starting the command, reading its output or another wrapper operation failed.

agent interfaceThe optional MCP server is not installed

optional MCP SDK. The isolated MCP Python environment is missing or cannot import the required SDK.