errors · bitdewfpga bit, nextpnr

design.sv:2: ERROR [wired-net]: a wor/wand net (declared at design.sv:2 and design.sv:3) with two drivers: yosys keeps the wired OR/AND as a $and cell, and nextpnr has nothing to place it on. Not a size problem. Fix: write the resolution yourself, in one assign: assign any = sw[3:0] | sw[7:4]; (wand: &), and declare the net as logic.

ERROR: Unable to place cell '$auto$hierarchy.cc:1470:execute$1744', no Bels remaining of type '$and'
design.sv:2: ERROR [wired-net]: a wor/wand net (declared at design.sv:2 and design.sv:3) with two drivers: yosys keeps the wired OR/AND as a $and cell, and nextpnr has nothing to place it on. Not a size problem. Fix: write the resolution yourself, in one assign:  assign any = sw[3:0] | sw[7:4];  (wand: &), and declare the net as logic. https://nosey-dewdrop.github.io/dewfpga/errors/wired-net/

Why does it happen?

Wired logic (wor, wand, trior, triand) resolves several drivers by OR or AND; yosys models that with a generic cell the Xilinx mapping does not know.

What is the fix?

logic [3:0] any;
assign any = sw[3:0] | sw[7:4];

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• a wor and a wand net, two drivers each

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.