SystemVerilog probes · 70Vivado: supported

a wor and a wand net, two drivers each

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.238): net types 'wand' and 'wor': Supported (tri0, tri1 and trireg are the unsupported ones)

What does the open-source chain do with it?

yosys keeps the wand and wor nets as $and and $or cells: the netlist is right, and nextpnr stops with 'no Bels remaining of type '$and'', which since #5 the CLI reads as 'design.sv:2: ERROR [wired-net]: a wor/wand net (declared at design.sv:2 and design.sv:3) with two drivers: yosys keeps the wired OR/AND as a $and cell, and nextpnr has nothing to place it on. Not a size problem. Fix: write the resolution yourself, in one assign: assign any = sw[3:0] | sw[7:4]; (wand: &), and declare the net as logic.' (before #5: the design does not fit the XC7A35T, for two gates)

Which error pages explain the messages?

• wired-net: A wor or wand net with several drivers; yosys keeps the wired resolution as a $and/$or cell nextpnr cannot place.

What is the probe's code?

From test/sv/70_wor_wand.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  wor  [3:0] any;                      // a wired-OR net: its two drivers are ORed
  wand [3:0] both;                     // a wired-AND net: ANDed
  assign any  = sw[3:0];
  assign any  = sw[7:4];
  assign both = sw[3:0];
  assign both = sw[7:4];
  assign led = {8'd0, both, any};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {i[3:0], i[7:4], i[7:0]}; #1
      if (!(led === {8'd0, sw[3:0] & sw[7:4], sw[3:0] | sw[7:4]})) begin $display("FAIL: wor and wand (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: disable of a named block to leave a loop (the lowest switch that is up)
next: one whole unpacked array assigned to another in always_ff: b <= a;