SystemVerilog probes · 69Vivado: supported

disable of a named block to leave a loop (the lowest switch that is up)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.238): 'disable: Supported'

What does the open-source chain do with it?

yosys: syntax error at disable (design.sv:7)

What is the probe's code?

From test/sv/69_disable.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  always_comb begin : find
    led = 16'd16;
    for (int i = 0; i < 16; i++)
      if (sw[i]) begin
        led = i;
        disable find;                  // leave the block at the lowest switch that is up
      end
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i, k; reg [15:0] want;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      want = 16'd16;
      for (k = 15; k >= 0; k = k - 1) if (sw[k]) want = k;
      if (!(led === want)) begin $display("FAIL: index of the lowest switch up (sw=%h led=%h want %h)", sw, led, want); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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