SystemVerilog probes · 68Vivado: supported

a slice of an unpacked array: b = a[2:3];

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Indexing and slicing of arrays: Supported', 'Array assignments: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:5: error: the type of the variable', and dewfpga sim goes on with 'design.sv:5: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:5: error: the type of the variable'; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/68_array_slice.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] a [0:3], b [0:1];
  always_comb begin
    for (int i = 0; i < 4; i++) a[i] = sw[4*i +: 4];
    b = a[2:3];                          // a slice of an unpacked array
    led = {8'd0, b[1], b[0]};
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {i[7:0], ~i[7:0]}; #1
      if (!(led === {8'd0, sw[15:8]})) begin $display("FAIL: b = a[2:3] (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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