patch notes · #284 October

#28 · dewfpga sim simulates what the build reads when iverilog refuses the design

The simulation no longer stops where the bitstream goes through. Of the 111 probes Vivado supports, 52 did not pass all four stages, and 28 of those failed only in dewfpga sim: iverilog does not read unique if, interfaces and modports, unpacked structs and unions, streaming, whole-array compare/copy/slice, a class used for its static function, the type operator and more, while the build read the same file and made a working bitstream. A student got a .bit from dewfpga bit and design.sv:7: ERROR [iverilog-refused]: iverilog cannot compile this code from dewfpga sim.

Now, when iverilog refuses a design file (not the testbench), sim runs the build's own front half, the same readers and the same checks as dewfpga bit, writes that design back as Verilog (top_sim.elab) and simulates it with the testbench and yosys' models of the Xilinx cells: design.sv:7: note [sim-from-build]: iverilog cannot compile this design (its lines are above), so the simulation runs on the design as the build reads it ..., then the testbench's own PASS. A design the build refuses is refused by sim too, with the build's line: a function with a ref argument, which yosys-slang silently drops, still stops instead of passing (measured: without that rule the second path printed the testbench's FAIL). A testbench iverilog cannot read gets the old error. What differs from simulating the source (delays inside the design are ignored, a testbench reference to an internal signal the build renamed can break) is on the new error page.

An independent review found one case this path got wrong: a testbench that sets the top module's parameters (top #(.W(2)) dut). The build keeps the defaults, so the elaborated design had no parameter left and iverilog blamed the student's testbench. Vivado's simulator applies those values; this path cannot, so it now stops at the testbench's line with [sim-from-build-parameters] and says why, instead of testing another design.

Numbers. Vivado-supported probes passing all four stages: 59/111 → 86/111; all four stages 64/133 → 95/133; synthesis 108/133 → 108/133. Known gaps: 52 → 25. Silent wrongs (bitstream built, netlist check fails): 3 → 3, the same rows (35, 74, 97). Closed in simulation: 31 probes (27 of them Vivado-supported). Not closed: 35 (no simulation model of MMCME2_BASE in yosys' cell library), 51c (the 2-D typedef scan stops before iverilog), 60 (a ref argument, refused on purpose). Blink's simulation is byte-identical and as fast as before; a design on the second path takes about 3 s instead of failing.

Tests. 6 new checks; each turns red when its rule is removed: the second path passes an interface design; a ref design is refused, not passed; a testbench iverilog cannot read keeps the old error; a design both readers refuse prints both; a testbench that sets parameters gets the new error at its line; blink's output is unchanged.

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The commands this entry names: dewfpga sim · dewfpga bit
Every SystemVerilog construct measured so far, next to what Vivado does: the probes, stage by stage