errors · simdewfpga sim, after iverilog refused a line of the design

design.sv:3: note [sim-from-build]: iverilog cannot compile this design (its lines are above), so the simulation runs on the design as the build reads it: read by yosys' own reader, written back as Verilog (top_sim.elab) and compiled with the testbench and yosys' models of the Xilinx cells. What differs: a # delay in the design is gone, an `ifdef SYNTHESIS branch is taken, and a signal the testbench reaches by its hierarchical name (dut.state) may be renamed or gone.

dewfpga sim on a design with a unique if, which iverilog 13 does not parse:

iverilog -g2012 -o top_sim design.sv tb.sv
design.sv:3: syntax error
design.sv:3: Syntax in assignment statement l-value.
design.sv:3: note [sim-from-build]: iverilog cannot compile this design (its lines are above), so the simulation runs on the design as the build reads it: read by yosys' own reader, written back as Verilog (top_sim.elab) and compiled with the testbench and yosys' models of the Xilinx cells. What differs: a # delay in the design is gone, an `ifdef SYNTHESIS branch is taken, and a signal the testbench reaches by its hierarchical name (dut.state) may be renamed or gone. https://nosey-dewdrop.github.io/dewfpga/errors/sim-from-build/
iverilog -g2012 -l /opt/homebrew/share/yosys/xilinx/cells_sim.v -o top_sim top_sim.elab tb.sv
PASS
tb.sv:12: $finish called at 8 (1s)

Why does it happen?

Icarus Verilog is the simulator, and it refuses SystemVerilog that Vivado and the build accept: unique if and priority if, a modport as a port type, an unpacked struct or union, streaming ({<<{...}}), an array compared, copied or sliced whole, a parameter of array type, type(), a static class member, a name used before its declaration, an assignment inside an expression, a $realtobits parameter. It also has no model of the Xilinx primitives (BUFG, and LUT2 or GND in a module the course hands out as a netlist). Before #28 dewfpga sim stopped there with iverilog-refused, while dewfpga bit built the design.

Now, when iverilog's first error is in a design file, dewfpga sim runs the build's front half, exactly as dewfpga bit does: the same scans (isunknown-in-design, package-file-not-given, ref-argument), yosys' own reader first and yosys-slang when it refuses, and the same checks on what they read (undeclared-name, two-always-drivers, async-reset-nonconst ...). The elaborated design the build leaves in top.il is written back as plain Verilog (top_sim.elab, next to your files; dewfpga clean removes it) and compiled with your testbench and yosys' simulation models of the Xilinx cells (cells_sim.v, as -l: a library, so only the cells your design uses are read). The note names the line iverilog refused and the reader that read the design.

A design the build refuses is refused here too, with the build's coded line and then iverilog's:

iverilog -g2012 -o top_sim design.sv tb.sv
design.sv:2: sorry: Reference ports not supported yet.
design.sv:2: error: Function tb.dut.inc port x is not an input port.
2 error(s) during elaboration.
design.sv:2: ERROR [ref-argument]: function inc takes an argument by reference (ref logic [3:0] x): yosys does not read ref, and yosys-slang drops it, so the variable it is called with would never change on the board. Fix: pass the value in and return it (function automatic logic [3:0] inc(input logic [3:0] x); ... return x + 1;  and  v = inc(v);). https://nosey-dewdrop.github.io/dewfpga/errors/ref-argument/
design.sv:2: ERROR [iverilog-refused]: iverilog cannot compile this code (its message is above), and the build refuses the design too (its lines are above). Fix: fix the first line it names; the errors after the first often follow from it. https://nosey-dewdrop.github.io/dewfpga/errors/iverilog-refused/

An error in the testbench is iverilog's verdict alone, as before: the second path is for the design.

What differs from simulating your source?

• A # delay inside the design is gone (synthesis has no delays); delays in the testbench stay.
• The design is read with SYNTHESIS defined, as Vivado and the build read it: an `ifdef SYNTHESIS branch is taken, an `ifndef SYNTHESIS block is dropped.
• Internal signals keep their names when they are declared (cnt, state), but a struct, an enum or an interface becomes plain vectors, and an expression's temporary gets a generated name (_3_): a hierarchical reference from the testbench (dut.state, dut.bus.a) may not find what it names. Check the ports instead, as the board does.
• A Xilinx cell without a simulation model (MMCME2_BASE) stops this path too; the error then says so.
• The top module's parameters are the defaults the build uses: a testbench that sets them (top #(.W(2)) dut) stops with sim-from-build-parameters.
• $display in the design still prints; $readmemh tables are built in.

What is the fix?

Nothing: the note says what ran. To make iverilog read the source itself, rewrite the construct it names (unique if as a plain if, a struct as separate signals, a copy of an array as a loop).

dewfpga sim

Which command prints it?

• dewfpga sim

Which probes in test/sv print this code?

• named assignment pattern '{hi: x, lo: y} and '{default: 0}
• an unpacked array concatenation: assign arr = {sw[3:0], sw[7:4]}; to logic [3:0] arr [0:1]
• a packed 2-D array indexed by a variable, then a bit or part select: grid[i][j] <= ... in a loop, grid[sw[13:12]][3:1]
• unique if / priority if
• unique0 if: an if/else if chain where no branch may match
• set membership: x inside {1,3,[8:10]} and case (x) inside
• an assignment within an expression: a = (b = sw[3:0]) + 4'd1; in always_comb
• interface with two modports, modport-typed module ports (sum_if.prod bus)
• an interface declared in its own file (sum_if.sv), generic interface ports
• a modport expression: modport lo (input .nib(data[3:0])); a submodule reads b.nib
• UNISIM primitive instantiation: BUFG
• gate primitives (not, and, or, xor) driving logic variables and an output logic port
• streaming concatenation: {<<{sw[7:0]}} (bit reverse) and {<<4{sw[15:8]}}
• iff event qualifier: always_ff @(posedge clk iff sw[15])
• an unpacked array localparam set with an assignment pattern: localparam logic [6:0] SEGS [0:3] = '{...}
• a packed 2-D localparam as a lookup table: localparam logic [3:0][6:0] SEG = {...}; seg = SEG[sw[1:0]];
• a name used before its declaration: assign led[0] = stop; logic stop;
• a conditional between two values of one enum: next = sw[0] ? RUN : IDLE;
• a course 'ready module' in netlist form in its own file ((* keep_hierarchy *), \<const0>, GND, LUT2), instantiated by the design
• the type operator: var type(a) b;
• an unpacked struct: typedef struct { logic [3:0] a; logic [3:0] b; } (no packed)
• an unpacked union: typedef union { logic [7:0] byte_v; logic [3:0] nib; } (no packed), one member written and read
• streaming concatenation as the target of an assignment: {>>{a, b}} = sw[7:0];
• equality of two whole unpacked arrays: a == b, a != b
• a slice of an unpacked array: b = a[2:3];
• one whole unpacked array assigned to another in always_ff: b <= a;
• a void function that returns through output arguments
• an unpacked array as a function argument
• $realtobits and $bitstoreal in localparams (a real turned into its IEEE 754 bits and back)
• a bitstream cast to an unpacked array: q = quad_t'(sw[7:0]); with typedef logic [3:0] quad_t [0:1]
• an extern module declaration ahead of the module: extern module inv4(input logic [3:0] a, output logic [3:0] y);
• a class used for its static function, called as util::rev(sw[3:0]) (no object is made)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.