errors · bitdewfpga bit, synthesis

note [read-with-slang]: top read with yosys-slang, the second reader (yosys' own reader refused this code; the build is the same from here).

note [read-with-slang]: top read with yosys-slang, the second reader (yosys' own reader refused this code; the build is the same from here). https://nosey-dewdrop.github.io/dewfpga/errors/read-with-slang/

Why does it happen?

Interfaces, unpacked arrays, foreach, break, hierarchical names, string parameters: SystemVerilog Vivado accepts and yosys' own reader does not. The second reader takes over, and the netlist is checked the same way.

Both readers read every file of the design as one compilation unit (yosys-slang with --single-unit, since 7 October 2026), the way Vivado reads the files of one library (UG901 Ch.10, Compilation Units): a typedef at file scope in types.sv is visible in iface.sv and design.sv, as it is in dewfpga sim (iverilog). Before that, yosys-slang read each file as its own unit and stopped with use of undeclared identifier 'nib_t' on a name another file declares.

What is the fix?

Nothing. The note says which reader built the design, in case a later message names a construct.

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• an interface with ports, interface cnt_if(input logic clk, input logic en), holding a counter; top reads c.q
• an array of interfaces: pair_if p [0:1] (); p[0].d and p[1].d driven and read in top
• an interface without ports whose members the module that instantiates it drives and reads: add_if bus (); assign bus.a = sw[7:0]; ... led = bus.s
• import in the module header: module top import pkg::*; (...)
• the same lookup table with its type named first: typedef logic [3:0][6:0] tab_t; localparam tab_t SEG = {...};
• a hierarchical name that reads a submodule's signal: assign led[1:0] = u_fsm.state;
• a parameter of type string: parameter string INIT_FILE = "digits.mem" (a ROM that takes its $readmemh file as a parameter)
• the same always_latch next to a foreach loop (43_foreach_loop), so the design is read with yosys-slang
• a package in its own file (pkg.sv: localparam, typedef, function), imported inside two modules in two files (design.sv, sub.sv), no `include anywhere
• two package files where a_pkg.sv imports z_pkg (declared in z_pkg.sv) and the design imports a_pkg::*; alphabetical order reads a_pkg.sv first

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.