SystemVerilog probes · 22fVivado: supported

an interface without ports whose members the module that instantiates it drives and reads: add_if bus (); assign bus.a = sw[7:0]; ... led = bus.s

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Interface syntax: Supported'; Ch.10 'Interfaces' (p.282-283) instantiates an interface in top (my_int int3();) and uses its members by name (int1.sel) only inside the submodules, through their interface port; that top uses them itself rests on Table 27 (p.288): 'Hierarchical names: Supported'

What does the open-source chain do with it?

bit: 'note [read-with-slang]: top read with yosys-slang, the second reader'

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/22f_interface_member_access.

design.sv

interface add_if;                         // no ports: a bundle that also adds
  logic [7:0] a, b, s;
  assign s = a + b;
endinterface
module top(input logic [15:0] sw, output logic [15:0] led);
  add_if bus ();
  assign bus.a = sw[7:0];                 // its members, from the module that instantiates it
  assign bus.b = sw[15:8];
  assign led = {8'd0, bus.s};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (led !== {8'd0, 8'(sw[7:0] + sw[15:8])}) begin $display("FAIL: sw=%h led=%h", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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