SystemVerilog probes · 22eVivado: supported

a modport expression: modport lo (input .nib(data[3:0])); a submodule reads b.nib

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Modport expressions: Supported' (IEEE 1800-2017 25.5.4, the .name(expression) form; slang's table of LRM clauses names 25.5.4 so)

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:5: syntax error', and dewfpga sim goes on with 'design.sv:5: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:5: syntax error'; bit: 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/22e_modport_expression.

design.sv

interface bus_if;
  logic [7:0] data;
  modport lo (input .nib(data[3:0]));   // a modport expression: nib is the low half of data
endinterface
module use_lo(bus_if.lo b, output logic [3:0] y);
  assign y = ~b.nib;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  bus_if bus();
  assign bus.data = sw[7:0];
  use_lo u_lo (.b(bus), .y(led[3:0]));
  assign led[15:4] = '0;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hA5, i[7:0]}; #1
      if (!(led === {12'd0, ~sw[3:0]})) begin $display("FAIL: the modport expression (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: an array of interfaces: pair_if p [0:1] (); p[0].d and p[1].d driven and read in top
next: an interface without ports whose members the module that instantiates it drives and reads: add_if bus (); assign bus.a = sw[7:0]; ... led = bus.s