SystemVerilog probes · 22dVivado: supported

an array of interfaces: pair_if p [0:1] (); p[0].d and p[1].d driven and read in top

Vivado: supported. The open-source chain: all four stages pass.

stagetoday
rtl, simulationpass
synth, synthesispass
netlist, the netlistpass
bit, the bitstreampass

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Array of interface: Supported'

What does the open-source chain do with it?

bit: 'note [read-with-slang]: top read with yosys-slang, the second reader'

Which error pages explain the messages?

What is the probe's code?

From test/sv/22d_interface_array.

design.sv

interface pair_if;
  logic [3:0] d;
endinterface
module top(input logic [15:0] sw, output logic [15:0] led);
  pair_if p [0:1] ();                    // an array of interfaces
  assign p[0].d = sw[3:0];
  assign p[1].d = sw[7:4];
  assign led = {8'd0, p[0].d, p[1].d};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hA5, i[7:0]}; #1
      if (!(led === {8'd0, sw[3:0], sw[7:4]})) begin $display("FAIL: the array of interfaces (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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