SystemVerilog probes · 22cVivado: supported

an interface with ports, interface cnt_if(input logic clk, input logic en), holding a counter; top reads c.q

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Ports in interfaces: Supported'

What does the open-source chain do with it?

bit: 'note [read-with-slang]: top read with yosys-slang, the second reader'

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/22c_interface_ports.

design.sv

interface cnt_if(input logic clk, input logic en);   // an interface with ports
  logic [3:0] q = 4'd0;
  always_ff @(posedge clk) if (en) q <= q + 4'd1;
endinterface
module top(input logic clk, input logic [15:0] sw, output logic [15:0] led);
  cnt_if c (.clk(clk), .en(sw[0]));
  assign led = {12'd0, c.q};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [3:0] want = 4'd0;
  integer i;
  top dut(.clk(clk), .sw(sw), .led(led));
  initial begin
    for (i = 0; i < 40; i = i + 1) begin
      sw = {15'd0, i % 3 != 0}; #1 clk = 1'b1; if (sw[0]) want = want + 4'd1; #1 clk = 1'b0; #1
      if (!(led === {12'd0, want})) begin $display("FAIL: the counter in the interface (i=%0d led=%h, want %h)", i, led, want); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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