SystemVerilog probes · 22bVivado: supported

an interface declared in its own file (sum_if.sv), generic interface ports

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Interface syntax: Supported'; the guide does not say which file an interface is declared in

What does the open-source chain do with it?

since #33 the CLI hands sum_if.sv first: rtl: iverilog refuses the generic interface port, 'design.sv:1: syntax error', and dewfpga sim goes on with 'design.sv:1: note [sim-from-build]' (the simulation runs on the design as yosys' own reader builds it), then 'PASS'; bit: yosys' own reader reads sum_if.sv then design.sv, 'pnr ok: 17 LUT, 0 FF, no clocked paths, timing not applicable'; netlist: the testbench prints PASS, the eqv half 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'. Before #33 (since #4): both readers refused, bit stopped with [undeclared-name] on sum_if

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.
• undeclared-name: A name used but never declared; yosys' reader makes an implicit 1-bit wire with no driver, so the design would be built without it.

What is the probe's code?

From test/sv/22b_interface_own_file.

design.sv

module producer(sum_if bus, input logic [7:0] in, output logic [4:0] res);   // sum_if lives in sum_if.sv
  assign bus.a = in[3:0];
  assign bus.b = in[7:4];
  assign res = bus.s;
endmodule
module consumer(sum_if bus);
  assign bus.s = bus.a + bus.b;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  sum_if bus();
  producer u_p (.bus(bus), .in(sw[7:0]), .res(led[4:0]));
  consumer u_c (.bus(bus));
  assign led[15:5] = '0;
endmodule

sum_if.sv

interface sum_if;
  logic [3:0] a, b;
  logic [4:0] s;
endinterface

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'h3C, i[7:0]}; #1
      if (!(led === {11'd0, 5'(sw[3:0] + sw[7:4])})) begin $display("FAIL: a + b through the interface (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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