errors · bitdewfpga bit, yosys

design.sv:4: ERROR [undeclared-name]: summ is not declared anywhere and nothing drives it: yosys made it a 1-bit wire stuck at x and built the design without it (dewfpga sim refuses this code). Fix: declare it, or check the spelling (a typo of a declared name).

design.sv:4: ERROR [undeclared-name]: summ is not declared anywhere and nothing drives it: yosys made it a 1-bit wire stuck at x and built the design without it (dewfpga sim refuses this code). Fix: declare it, or check the spelling (a typo of a declared name). https://nosey-dewdrop.github.io/dewfpga/errors/undeclared-name/
yosys-slang: design.sv:4:21: error: use of undeclared identifier 'summ'; did you mean 'sum'?

Why does it happen?

Verilog's implicit nets: an undeclared name on a port connection or the right of an assign becomes a 1-bit wire. yosys warns and goes on; the CLI turns the warning into a stop when nothing drives that wire. yosys-slang, the second reader, often suggests the intended name.

A second cause: the name is a typedef at file scope (outside any module or package) in a file the readers have not read when they reach the use. Both readers read every .sv and .v of the folder as one compilation unit, the files that hold no module (a package, an interface, typedefs alone in their file) first, then the files that hold a module, as Vivado reads the files of one library (UG901 Ch.10, Compilation Units). A .svh or .vh reaches them only through an `include. The message then names the file that declares the typedef and whether it is read too late or not at all:

iface.sv:2: ERROR [undeclared-name]: nib_t is a typedef declared in types.svh at file scope (outside any module or package), and no file `includes types.svh, so the readers never see it (a .svh or .vh reaches them only through an `include); Vivado reads the files of one library as one compilation unit, in the order they are added (UG901 Ch.10 Compilation Units), and so do both readers here. Fix: add   `include "types.svh"   as the first line of iface.sv; or put the typedef in a package (package types_pkg; typedef ...; endpackage) and write  import types_pkg::*;  where it is used. https://nosey-dewdrop.github.io/dewfpga/errors/undeclared-name/

What is the fix?

Fix the spelling, or declare the signal:

assign led[3:0] = sum;

For a typedef in another file: `include that file as the first line of the file that uses the type, or put the typedef in a package and import it where it is used. A typedef in its own types.sv next to the design needs neither: that file is read first.

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• an interface declared in its own file (sum_if.sv), generic interface ports
• a typo: an undeclared name on the right of an assign (summ for sum)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.