SystemVerilog probes · 39Vivado: unverified

a typo: an undeclared name on the right of an assign (summ for sum)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. IEEE 1800-2017 6.10: an undeclared name becomes an implicit net only in a port connection, a primitive terminal or on the left of a continuous assignment, so this use is an error; iverilog 13 rejects it. No Vivado log of this case in the corpus

What does the open-source chain do with it?

since #5; rtl: iverilog refuses it, 'design.sv:4: error: Unable to bind wire/reg/memory', and since #28 dewfpga sim runs the build's front half, which refuses it with the same coded line as bit, then adds 'design.sv:4: ERROR [iverilog-refused]: iverilog cannot compile this code (its message is above), and the build refuses the design too (its lines are above). Fix: fix the first line it names; the errors after the first often follow from it.'; bit: 'design.sv:4: ERROR [undeclared-name]: summ is not declared anywhere and nothing drives it: yosys made it a 1-bit wire stuck at x and built the design without it (dewfpga sim refuses this code). Fix: declare it, or check the spelling (a typo of a declared name).'; yosys-slang: 'design.sv:4:21: error: use of undeclared identifier'

Which error pages explain the messages?

• iverilog-refused: iverilog stopped with an error; its own lines are above, and this line names the first of them.
• undeclared-name: A name used but never declared; yosys' reader makes an implicit 1-bit wire with no driver, so the design would be built without it.

What is the probe's code?

From test/sv/39_undeclared_name.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] sum;
  assign sum = sw[3:0] + sw[7:4];
  assign led[3:0] = summ;               // typo: summ is never declared
  assign led[15:4] = '0;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'h00, i[7:0]}; #1
      if (!(led === {12'd0, 4'(sw[3:0] + sw[7:4])})) begin $display("FAIL: sum (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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