SystemVerilog probes · 40Vivado: supported

a module named display next to a $display call in a design module

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Any identifier can name a module (IEEE 1800-2017 A.1.2). UG901 v2023.2 Ch.9 Table 21 (p.239): '$display: Limited Support', and 'Vivado synthesis ignores unsupported system tasks'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/40_display_module_name.

design.sv

module display(input logic [3:0] x, output logic [6:0] seg);   // a natural name for a 7-segment module
  assign seg = {x[0], x[1], x[2], x[3], ^x, &x, |x};
endmodule
module top(input logic [15:0] sw, output logic [15:0] led, output logic [6:0] seg);
  display u_disp (.x(sw[3:0]), .seg(seg));
  assign led = sw;
  initial $display("top: display loaded");   // a debug print in the design, next to a module named display
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg;
  integer i;
  top dut(.sw(sw), .led(led), .seg(seg));
  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      sw = {12'hA5C, i[3:0]}; #1
      if (!(led === sw && seg === {sw[0], sw[1], sw[2], sw[3], ^sw[3:0], &sw[3:0], |sw[3:0]})) begin $display("FAIL: display (sw=%h seg=%b)", sw, seg); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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