SystemVerilog probes · 40bVivado: supported

a module name and ( inside a $display string in a design module: $display("counter (u_cnt) wrapped") next to module counter

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.239): '$display: Limited Support', and 'Vivado synthesis ignores unsupported system tasks.'; the text of a string literal is not code (IEEE 1800-2017 5.9)

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/40b_module_name_in_string.

design.sv

module counter(input logic clk, input logic rst, output logic [3:0] q);
  always_ff @(posedge clk) if (rst) q <= '0; else q <= q + 4'd1;
endmodule
module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] q;
  counter u_cnt (.clk(clk), .rst(btnC), .q(q));
  always @(posedge clk) if (q == 4'hf) $display("counter (u_cnt) wrapped");   // a module name and ( in a string
  assign led = {sw[15:4], q};
endmodule

tb.sv

module tb;
  logic clk = 0, btnC = 1; logic [15:0] sw = 16'ha5a5; logic [15:0] led;
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  integer i, bad = 0;
  initial begin
    #5 clk = 1; #5 clk = 0; btnC = 0;
    for (i = 1; i <= 40; i++) begin
      #5 clk = 1; #5 clk = 0;
      if (led !== {sw[15:4], i[3:0]}) begin bad++; if (bad < 4) $display("FAIL: after %0d edges led=%h", i, led); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 40", bad);
    $finish;
  end
endmodule

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