SystemVerilog probes · 41Vivado: supported

wildcard equality: sw[7:0] ==? 8'b1??0_??01 and !=?

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Wildcard equality operators: Supported'

What does the open-source chain do with it?

since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); rtl: PASS; bit: 'pnr ok: 2 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV PASS: 1048576 output bits compared, all equal'

What is the probe's code?

From test/sv/41_wildcard_equality.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[0] = (sw[7:0] ==? 8'b1??0_??01);    // wildcard equality: a ? bit on the right matches anything
  assign led[1] = (sw[15:8] !=? 8'b??11_0???);   // wildcard inequality
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i; reg w0, w1;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      w0 = sw[7] & ~sw[4] & ~sw[1] & sw[0];
      w1 = ~(sw[13] & sw[12] & ~sw[11]);
      if (!(led === {14'd0, w1, w0})) begin $display("FAIL: ==? and !=? (sw=%h led=%h want %b%b)", sw, led, w1, w0); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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