SystemVerilog probes · 42Vivado: not supported

streaming concatenation: {<<{sw[7:0]}} (bit reverse) and {<<4{sw[15:8]}}

Vivado: not supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Not supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Re-ordering of the generic stream: Not Supported', and {<<{...}} is that re-ordering (right to left, one bit or four bits at a time). The row above it (p.286), 'Concatenation of stream_expressions: Supported', is the stream without re-ordering; UG901 v2022.2 Table 8-1 (p.289) says the same. No Vivado log in the corpus (it has no {<<)

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:2: sorry: Streaming concatenation not supported.', and dewfpga sim goes on with 'design.sv:2: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:2: sorry: Streaming concatenation not supported.'; bit: 'pnr ok: 0 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/42_streaming_concat.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[7:0]  = {<<{sw[7:0]}};     // streaming concatenation: the bits in reverse order
  assign led[15:8] = {<<4{sw[15:8]}};   // slices of 4: the two nibbles swapped
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i, b; reg [7:0] rev;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      for (b = 0; b < 8; b = b + 1) rev[b] = sw[7 - b];
      if (!(led === {sw[11:8], sw[15:12], rev})) begin $display("FAIL: {<<{}} and {<<4{}} (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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