errors · simdewfpga sim, iverilog

design.sv:4: ERROR [iverilog-refused]: iverilog cannot compile this code (its message is above). Fix: fix the first line it names; the errors after the first often follow from it.

iverilog -g2012 -o top_sim design.sv tb.sv
design.sv:4: error: Unable to bind wire/reg/memory `summ' in `tb.dut'
design.sv:4: error: Unable to elaborate r-value: summ
2 error(s) during elaboration.
design.sv:4: ERROR [iverilog-refused]: iverilog cannot compile this code (its message is above). Fix: fix the first line it names; the errors after the first often follow from it. https://nosey-dewdrop.github.io/dewfpga/errors/iverilog-refused/

Why does it happen?

A syntax error, an undeclared name (summ above: a typo of sum), or a construct iverilog does not support (sorry: ...). One mistake often produces several lines.

What is the fix?

Read iverilog's first line and fix that; run again. sorry: lines name constructs iverilog lacks; the guide's section 8 lists them.

dewfpga sim

Since #28, when the line iverilog names is in a design file (not the testbench), dewfpga sim goes on: it builds the design the way dewfpga bit reads it and simulates that, with a note [sim-from-build]. This error then comes only when the build refuses the design too (the build's own coded line is above it), or when the testbench is what iverilog cannot compile.

Which command prints it?

Which probes in test/sv print this code?

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.