SystemVerilog probes · 38Vivado: supported

gate primitives (not, and, or, xor) driving logic variables and an output logic port

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2015.2 logs of a public CS223 lab repo: internal logic signals and an output logic port driven by or gate primitives, synthesis 'Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.', implementation 'Bitgen Completed Successfully.'. UG901 v2023.2 Ch.9 'Verilog Primitives' (p.242): 'Vivado synthesis supports Verilog gate-level primitives except as shown in the following table.' (that table: pullup/pulldown, arrays of primitives)

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:3: error: Variable 'ns' cannot be driven by a primitive or continuous assignment', and dewfpga sim goes on with 'design.sv:3: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: "Variable 'ns' cannot be driven by a primitive or continuous assignment with non-default strength." (design.sv:3); yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/38_gate_primitives.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic ns, t0, t1;                     // logic variables driven by gate primitives (CS223 structural labs)
  not g0 (ns, sw[2]);
  and g1 (t0, sw[0], ns);
  and g2 (t1, sw[1], sw[2]);
  or  g3 (led[0], t0, t1);              // an output logic port driven by a primitive: a 2-to-1 mux
  xor g4 (led[1], sw[3], sw[4], sw[5]);
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 64; i = i + 1) begin
      sw = {10'h2AA, i[5:0]}; #1
      if (!(led === {14'd0, sw[3] ^ sw[4] ^ sw[5], sw[2] ? sw[1] : sw[0]})) begin $display("FAIL: gates (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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