SystemVerilog probes · 37bVivado: unverified

a variable declared with an initializer that reads inputs: logic [3:0] sum = sw[3:0] + sw[7:4]; (meant as an adder)

Vivado: unverified. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Variable declaration assignment (variable initialization): Supported', and Ch.9 'Initial Values' (p.244) describes a constant start value; the guide does not say what Vivado does with an initializer that reads an input. IEEE 1800-2017 6.8: a variable declaration assignment sets the start value once, before any process runs; a net declaration assignment (wire) is continuous

What does the open-source chain do with it?

the scanner sees a declaration initializer that reads a port and stops sim and bit before make: 'design.sv:2: ERROR [decl-init-reads-signal]:' then 'in a declaration is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8; yosys makes it the power-up value, so the board never follows sw). Fix: write assign sum = sw[3:0] + sw[7:4]; and declare sum without the = part.'; no bitstream. A constant start value (logic [3:0] cnt = 4'd5;) still passes (37_var_init)

Which error pages explain the messages?

• decl-init-reads-signal: `logic [3:0] sum = sw[3:0] + sw[7:4];` sets a power-up value from a signal; it is not a continuous assignment, and the board would show the value from time 0 forever.

What is the probe's code?

From test/sv/37b_decl_init_expr.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] sum = sw[3:0] + sw[7:4];    // meant as the sum of two nibbles; the standard makes it a start value
  assign led = {12'd0, sum};
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [15:0] first;
  integer i;
  top dut(.sw(sw), .led(led));
  // IEEE 1800-2017 6.8: a variable's declaration assignment sets its start value once, before any process
  // runs, so sum does not follow sw afterwards
  initial begin
    #1 first = led;
    for (i = 1; i < 256; i = i + 1) begin
      sw = i * 16'h0101; #1
      if (led !== first) begin $display("FAIL: led follows sw (sw=%h led=%h, was %h): an initializer runs once", sw, led, first); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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