errors · bitdewfpga sim / bit, the source scan before the tools run

design.sv:2: ERROR [decl-init-reads-signal]: `sum = sw[3:0] + sw[7:4]` in a declaration is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8; yosys makes it the power-up value, so the board never follows sw). Fix: write assign sum = sw[3:0] + sw[7:4]; and declare sum without the = part.

design.sv:2: ERROR [decl-init-reads-signal]: `sum = sw[3:0] + sw[7:4]` in a declaration is a start value, not a wire: it reads sw once, at time 0 (IEEE 1800-2017 6.8; yosys makes it the power-up value, so the board never follows sw). Fix: write  assign sum = sw[3:0] + sw[7:4];  and declare sum without the = part. https://nosey-dewdrop.github.io/dewfpga/errors/decl-init-reads-signal/

Why does it happen?

type name = expr; in a declaration is an initializer: evaluated once when the simulation starts (IEEE 1800-2017 6.8). The simulation looks right when the inputs never change; on the board the register keeps the value it was configured with and never follows the switches.

What is the fix?

A wire is a continuous assignment; a register is loaded in an always block:

logic [3:0] sum;
assign sum = sw[3:0] + sw[7:4];

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• a variable declared with an initializer that reads inputs: logic [3:0] sum = sw[3:0] + sw[7:4]; (meant as an adder)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.