SystemVerilog probes · 37Vivado: unverified

register power-up value: logic [3:0] cnt = 5; and initial c2 = 9;

Vivado: unverified. The open-source chain: all four stages pass.

What does Vivado do with it?

Unverified. UG901 v2023.2 Ch.9 'Initial Values' (p.244): 'When you assign a register as an initial value in a declaration, Vivado synthesis sets this value on the output of the register at global reset or power up' covers cnt. For initial c2 = 9 the guide contradicts itself: Ch.9 (p.251) 'initial blocks are ignored during synthesis', Ch.5 (p.155) initializes a RAM with 'initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/37_var_init.

design.sv

module top(input logic clk, output logic [15:0] led);
  logic [3:0] cnt = 4'd5;       // declaration initializer = power-up value
  logic [3:0] c2;
  initial c2 = 4'd9;             // initial block = power-up value
  always_ff @(posedge clk) begin
    cnt <= cnt + 4'd1;
    c2  <= c2 - 4'd1;
  end
  assign led = {8'd0, c2, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .led(led));
  initial begin
    #1
    if (!(led === 16'h0095)) begin $display("FAIL: power-up values (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    tick;
    if (!(led === 16'h0086)) begin $display("FAIL: after one clock (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: (* keep = "true" *) and (* dont_touch = "true" *) on internal nets
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