SystemVerilog probes · 36Vivado: supported

(* keep = "true" *) and (* dont_touch = "true" *) on internal nets

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.3 'Synthesis Attributes': 'DONT_TOUCH' (p.51), 'KEEP' (p.59)

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/36_keep_attr.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  (* keep = "true" *)       logic mid;
  (* dont_touch = "true" *) logic mid2;
  assign mid  = sw[0] & sw[1];
  assign mid2 = sw[2] | sw[3];
  assign led[0] = mid | sw[2];
  assign led[1] = mid2 ^ sw[4];
  assign led[15:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0003; #1
    if (!(led === 16'h0001)) begin $display("FAIL: vector 1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0014; #1
    if (!(led === 16'h0001)) begin $display("FAIL: vector 2 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0010; #1
    if (!(led === 16'h0002)) begin $display("FAIL: vector 3 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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