SystemVerilog probes · 35Vivado: supported

UNISIM MMCME2_BASE (100 to 50 MHz) + BUFG

Vivado: supported. The open-source chain: it builds a bitstream, and the netlist check fails.

What does Vivado do with it?

Supported. UG953 v2022.2 Ch.5 MMCME2_BASE (p.459): 'Design Entry Method: Instantiation: Yes' (IP Catalog: Recommended); UG901 v2023.2 Ch.9 (p.232): AMD primitives are instantiated from unisim_comp.v

What does the open-source chain do with it?

rtl and netlist: no MMCME2_BASE model in iverilog or in yosys' cells_sim.v; the bitstream is built but not checked on a board

What is the probe's code?

From test/sv/35_mmcm.

design.sv

module top(input logic clk, input logic btnC, output logic [15:0] led);
  logic clk_fb, clk_out, clk50, locked;
  logic [7:0] cnt;
  MMCME2_BASE #(.CLKIN1_PERIOD(10.0), .CLKFBOUT_MULT_F(10.0), .DIVCLK_DIVIDE(1), .CLKOUT0_DIVIDE_F(20.0))
    u_mmcm (.CLKIN1(clk), .CLKFBIN(clk_fb), .CLKFBOUT(clk_fb), .CLKOUT0(clk_out), .LOCKED(locked),
            .PWRDWN(1'b0), .RST(btnC),
            .CLKFBOUTB(), .CLKOUT0B(), .CLKOUT1(), .CLKOUT1B(), .CLKOUT2(), .CLKOUT2B(),
            .CLKOUT3(), .CLKOUT3B(), .CLKOUT4(), .CLKOUT5(), .CLKOUT6());
  BUFG u_bufg (.I(clk_out), .O(clk50));
  always_ff @(posedge clk50 or negedge locked)
    if (!locked) cnt <= '0; else cnt <= cnt + 8'd1;
  assign led = {locked, 7'd0, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .led(led));
  initial begin
    btnC = 1; repeat (10) tick; btnC = 0; repeat (5000) tick;
    if (!(led[15] === 1'b1 && led[7:0] !== 8'd0)) begin $display("FAIL: MMCM locked and 50 MHz counter running (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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