SystemVerilog probes · 34Vivado: supported

UNISIM primitive instantiation: BUFG

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 'Instantiating Pre-Defined Primitives' (p.231-232): 'AMD-specific primitives such as CLKDLL and BUFG ... The unisim_comp.v library file includes the definitions for FDC and BUFG'; UG953 v2022.2 Ch.5 BUFG (p.266): 'Instantiation: Yes'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:4: error: Unknown module type: BUFG', and dewfpga sim goes on with 'design.sv:4: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog alone has no BUFG model; the second path compiles the elaborated design with yosys' cells_sim.v, which has one

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/34_bufg.

design.sv

module top(input logic clk, input logic btnC, output logic [15:0] led);
  logic clk_g;
  logic [3:0] cnt;
  BUFG u_bufg (.I(clk), .O(clk_g));
  always_ff @(posedge clk_g)
    if (btnC) cnt <= '0; else cnt <= cnt + 4'd1;
  assign led = {12'd0, cnt};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; tick; tick; tick;
    if (!(led[3:0] === 4'd3)) begin $display("FAIL: counter on BUFG clock (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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