SystemVerilog probes · 22Vivado: supported

interface with two modports, modport-typed module ports (sum_if.prod bus)

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.288): 'Interface syntax: Supported'; Ch.10 'Modports' (p.283-284): 'To specify the direction, use the modport keyword', with modport b1 (input result, output sel, data1, data2); and a module port my_int.b1 int1, the form this probe uses (plain modports; the .name(expression) form is 22e)

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:7: syntax error', and dewfpga sim goes on with 'design.sv:7: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: syntax error at the modport port (design.sv:7)

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/22_interface_modport.

design.sv

interface sum_if;
  logic [3:0] a, b;
  logic [4:0] s;
  modport prod (output a, b, input s);
  modport cons (input a, b, output s);
endinterface
module producer(sum_if.prod bus, input logic [7:0] in, output logic [4:0] res);
  assign bus.a = in[3:0];
  assign bus.b = in[7:4];
  assign res = bus.s;
endmodule
module consumer(sum_if.cons bus);
  assign bus.s = bus.a + bus.b;
endmodule
module top(input logic [15:0] sw, output logic [15:0] led);
  sum_if bus();
  producer u_p (.bus(bus), .in(sw[7:0]), .res(led[4:0]));
  consumer u_c (.bus(bus));
  assign led[15:5] = '0;
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'hA5, i[7:0]}; #1
      if (!(led === {11'd0, 5'(sw[3:0] + sw[7:4])})) begin $display("FAIL: a + b through the interface (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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