SystemVerilog probes · 21bVivado: supported

an assignment within an expression: a = (b = sw[3:0]) + 4'd1; in always_comb

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Assignment within an expression: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:4: syntax error', and dewfpga sim goes on with 'design.sv:4: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; iverilog 13 alone: syntax error at the assignment inside the expression (design.sv:4), 'Malformed statement'; yosys builds it; netlist: testbench only, eqv.sh cannot compile the RTL with iverilog

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/21b_assign_in_expr.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  logic [3:0] a, b;
  always_comb begin
    a = (b = sw[3:0]) + 4'd1;             // an assignment within an expression: b gets sw[3:0], a gets b + 1
    led = {8'd0, a, b};
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 16; i = i + 1) begin
      sw = {12'hA5C, i[3:0]}; #1
      if (!(led === {8'd0, 4'(sw[3:0] + 4'd1), sw[3:0]})) begin $display("FAIL: assignment within an expression (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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