SystemVerilog probes · 21Vivado: supported

x++ and x += in always_comb, k++ inside always_ff, for (int i..;i++) with c++

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.286): 'Assignment operators', 'Increment and decrement operators': Supported

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/21_incdec_assignops.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  logic [7:0] cnt, acc, nxt_cnt, nxt_acc;
  logic [3:0] k;
  logic [4:0] c;
  always_comb begin
    nxt_cnt = cnt; nxt_cnt++;
    nxt_acc = acc; nxt_acc += {4'd0, sw[3:0]};
  end
  always_ff @(posedge clk)
    if (btnC) begin cnt <= '0; acc <= '0; end
    else begin cnt <= nxt_cnt; acc <= nxt_acc; end
  always_ff @(posedge clk)
    if (btnC) k <= '0; else k++;              // student style: ++ inside always_ff
  always_comb begin
    c = '0;
    for (int i = 0; i < 16; i++) if (sw[i]) c++;
  end
  assign led = {k, c[3:0], acc[3:0], cnt[3:0]};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0; sw = 16'h0003; tick; tick; tick;
    if (!(led === 16'h3293)) begin $display("FAIL: cnt=3 acc=9 popcount=2 k=3 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

previous: set membership: x inside {1,3,[8:10]} and case (x) inside
next: an assignment within an expression: a = (b = sw[3:0]) + 4'd1; in always_comb