SystemVerilog probes · 20Vivado: not supported

set membership: x inside {1,3,[8:10]} and case (x) inside

Vivado: not supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Not supported. UG901 v2023.2 Ch.10 Table 27 (p.287): 'Set membership operator: Not Supported', 'Set membership case statement: Not Supported'; the same in UG901 v2022.2 Table 8-1. Whether a newer Vivado accepts it: unverified

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:3: sorry:' (inside expressions, not supported yet), and dewfpga sim goes on with 'design.sv:3: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:3: sorry:' (inside expressions, not supported yet); bit: 'pnr ok: 3 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/20_inside.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  always_comb begin
    led[0] = sw[3:0] inside {4'd1, 4'd3, [4'd8:4'd10]};
    case (sw[7:4]) inside
      4'd0, 4'd1:  led[2:1] = 2'd1;
      [4'd2:4'd7]: led[2:1] = 2'd2;
      default:     led[2:1] = 2'd3;
    endcase
    led[15:3] = '0;
  end
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.sw(sw), .led(led));
  initial begin
    sw = 16'h0009; #1
    if (!(led === 16'h0003)) begin $display("FAIL: 9 inside, 0 -> 1 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h0054; #1
    if (!(led === 16'h0004)) begin $display("FAIL: 4 not inside, 5 -> 2 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    sw = 16'h00F3; #1
    if (!(led === 16'h0007)) begin $display("FAIL: 3 inside, F -> 3 (led=%h seg=%b an=%b)", led, seg, an); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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