SystemVerilog probes · 19Vivado: supported

casez with ? wildcards, casex

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 'Case Statement' (p.279): 'there are also the casex and casez statements'

What does the open-source chain do with it?

All four stages pass; expect.tsv records no message for this probe.

What is the probe's code?

From test/sv/19_casez_casex.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  always_comb begin
    casez (sw[3:0])
      4'b1???: led[1:0] = 2'd3;
      4'b01??: led[1:0] = 2'd2;
      4'b001?: led[1:0] = 2'd1;
      default: led[1:0] = 2'd0;
    endcase
    casex (sw[7:4])
      4'b1xx0: led[2] = 1'b1;
      default: led[2] = 1'b0;
    endcase
    led[15:3] = '0;
  end
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  reg [1:0] z;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 256; i = i + 1) begin
      sw = {8'h3C, i[7:0]}; #1
      z = sw[3] ? 2'd3 : sw[2] ? 2'd2 : sw[1] ? 2'd1 : 2'd0;      // casez: ? matches anything
      if (!(led === {13'd0, sw[7] & ~sw[4], z})) begin $display("FAIL: casez / casex (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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