SystemVerilog probes · 51cVivado: supported

the same lookup table with its type named first: typedef logic [3:0][6:0] tab_t; localparam tab_t SEG = {...};

Vivado: supported. The open-source chain: it builds, and fails in simulation.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'User-defined types', 'Packed arrays', 'Multidimensional arrays', 'Indexing and slicing of arrays': Supported

What does the open-source chain do with it?

bit: 'note [read-with-slang]: top read with yosys-slang, the second reader'; rtl: the typedef scan stops dewfpga sim before iverilog: 'design.sv:4: ERROR [packed-typedef-2d]: SEG is declared with the type tab_t, a packed array with two dimensions (design.sv:3): yosys keeps a value of such a typedef as one flat vector, so SEG[i] picks one bit instead of one row, and the table would be built wrong.'

Which error pages explain the messages?

• packed-typedef-2d: A typedef of a two-dimensional packed array used to declare a parameter or a net; yosys flattens the type and every row index picks one bit.
• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/51c_packed_param_typedef.

design.sv

module top(input logic [15:0] sw, output logic [6:0] seg, output logic [3:0] an);
  // the same table as 51b, its type named first: a typedef of the packed 2-D array
  typedef logic [3:0][6:0] tab_t;
  localparam tab_t SEG = {7'b0110000, 7'b0100100, 7'b1111001, 7'b1000000};
  assign seg = SEG[sw[1:0]];
  assign an  = 4'b1110;
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [6:0] seg; logic [3:0] an;
  top dut(.sw(sw), .seg(seg), .an(an));
  logic [6:0] want [0:3] = '{7'b1000000, 7'b1111001, 7'b0100100, 7'b0110000};   // 0, 1, 2, 3
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 64; i++) begin
      sw = i; #1;
      if (seg !== want[sw[1:0]] || an !== 4'b1110) begin bad++; if (bad < 4) $display("FAIL: sw=%h seg=%b", sw, seg); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 64", bad);
    $finish;
  end
endmodule

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