errors · bitdewfpga sim / bit, the typedef scan before the tools run

design.sv:4: ERROR [packed-typedef-2d]: SEG is declared with the type tab_t, a packed array with two dimensions (design.sv:3): yosys keeps a value of such a typedef as one flat vector, so SEG[i] picks one bit instead of one row, and the table would be built wrong. Fix: write the dimensions on the declaration itself: logic [3:0][6:0] SEG; a parameter yosys refuses in that form, so keep it flat and take a row with +: (localparam logic [N*W-1:0] SEG = {...}; SEG[i*W +: W]).

design.sv:4: ERROR [packed-typedef-2d]: SEG is declared with the type tab_t, a packed array with two dimensions (design.sv:3): yosys keeps a value of such a typedef as one flat vector, so SEG[i] picks one bit instead of one row, and the table would be built wrong. Fix: write the dimensions on the declaration itself:  logic [3:0][6:0] SEG;  a parameter yosys refuses in that form, so keep it flat and take a row with +:  (localparam logic [N*W-1:0] SEG = {...}; SEG[i*W +: W]). https://nosey-dewdrop.github.io/dewfpga/errors/packed-typedef-2d/

Why does it happen?

typedef logic [3:0][6:0] tab_t; is fine in Vivado and iverilog. yosys' own reader keeps a value of such a typedef as a 28-bit vector, so SEG[1] is bit 1, not row 1, and the table is silently wrong on the board. The scan refuses it before either reader runs.

What is the fix?

Put the dimensions on the declaration; for a parameter keep it flat and slice with +::

localparam logic [4*7-1:0] SEG = {7'h7F, 7'h06, 7'h5B, 7'h4F};
assign seg = SEG[i*7 +: 7];

Which command prints it?

• dewfpga sim
• dewfpga bit

Which probes in test/sv print this code?

• the same lookup table with its type named first: typedef logic [3:0][6:0] tab_t; localparam tab_t SEG = {...};

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.