SystemVerilog probes · 51bVivado: supported

a packed 2-D localparam as a lookup table: localparam logic [3:0][6:0] SEG = {...}; seg = SEG[sw[1:0]];

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Packed arrays', 'Multidimensional arrays', 'Indexing and slicing of arrays': Supported

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:3: sorry: packed array parameters are not supported yet.', and dewfpga sim goes on with 'design.sv:3: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:3: sorry: packed array parameters are not supported yet.'; bit: 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/51b_packed_param_array.

design.sv

module top(input logic [15:0] sw, output logic [6:0] seg, output logic [3:0] an);
  // the digits 0-3 as seven-segment patterns (active low), one packed 2-D localparam
  localparam logic [3:0][6:0] SEG = {7'b0110000, 7'b0100100, 7'b1111001, 7'b1000000};
  assign seg = SEG[sw[1:0]];
  assign an  = 4'b1110;
endmodule

tb.sv

module tb;
  logic [15:0] sw; logic [6:0] seg; logic [3:0] an;
  top dut(.sw(sw), .seg(seg), .an(an));
  logic [6:0] want [0:3] = '{7'b1000000, 7'b1111001, 7'b0100100, 7'b0110000};   // 0, 1, 2, 3
  integer i, bad = 0;
  initial begin
    for (i = 0; i < 64; i++) begin
      sw = i; #1;
      if (seg !== want[sw[1:0]] || an !== 4'b1110) begin bad++; if (bad < 4) $display("FAIL: sw=%h seg=%b", sw, seg); end
    end
    if (bad == 0) $display("PASS"); else $display("FAIL: %0d of 64", bad);
    $finish;
  end
endmodule

previous: an unpacked array localparam set with an assignment pattern: localparam logic [6:0] SEGS [0:3] = '{...}
next: the same lookup table with its type named first: typedef logic [3:0][6:0] tab_t; localparam tab_t SEG = {...};