SystemVerilog probes · 51Vivado: supported

an unpacked array localparam set with an assignment pattern: localparam logic [6:0] SEGS [0:3] = '{...}

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 Table 27 (p.285): 'Unpacked arrays: Supported'; (p.286): 'Array assignment patterns: Supported'

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'design.sv:2: sorry: unpacked array parameters are not supported yet.', and dewfpga sim goes on with 'design.sv:2: note [sim-from-build]' (the simulation runs on the design as the build reads it, 'read by yosys-slang, the second reader', written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'; since #4; built by yosys-slang, yosys' own reader refused this code (the note in bit.log); iverilog alone refuses it, 'design.sv:2: sorry: unpacked array parameters are not supported yet.'; bit: 'pnr ok: 4 LUT, 0 FF, no clocked paths, timing not applicable (full log: top.log)'; netlist: PASS, 'EQV SKIP: iverilog cannot compile the RTL, so only the testbench checked the netlist'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/51_unpacked_param_array.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  localparam logic [6:0] SEGS [0:3] = '{7'h40, 7'h79, 7'h24, 7'h30};   // an unpacked array constant, 0 to 3 on a 7-segment digit
  assign led = {9'b0, SEGS[sw[1:0]]};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i; reg [6:0] want;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      case (sw[1:0]) 0: want = 7'h40; 1: want = 7'h79; 2: want = 7'h24; default: want = 7'h30; endcase
      if (!(led === {9'd0, want})) begin $display("FAIL: SEGS[sw[1:0]] (sw=%h led=%h want %h)", sw, led, want); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: function arguments bound by name, in another order: diff(.b(x), .a(y))
next: a packed 2-D localparam as a lookup table: localparam logic [3:0][6:0] SEG = {...}; seg = SEG[sw[1:0]];