SystemVerilog probes · 58Vivado: supported

a hierarchical name that reads a submodule's signal: assign led[1:0] = u_fsm.state;

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 20 (p.239): 'hierarchical names: Supported'; Ch.10 Table 27 (p.288): 'Hierarchical names: Supported'

What does the open-source chain do with it?

bit: 'note [read-with-slang]: top read with yosys-slang, the second reader'

Which error pages explain the messages?

• read-with-slang: Not an error: yosys' own reader refused the code, yosys-slang read it, and synthesis went on as usual.

What is the probe's code?

From test/sv/58_hier_name.

design.sv

module fsm(input logic clk, input logic reset, input logic go, output logic busy);
  typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;
  state_t state;
  always_ff @(posedge clk, posedge reset)
    if (reset) state <= IDLE;
    else case (state)
      IDLE:    if (go) state <= RUN;
      RUN:     state <= DONE;
      default: state <= IDLE;
    endcase
  assign busy = (state == RUN);
endmodule
module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  fsm u_fsm (.clk(clk), .reset(btnC), .go(sw[0]), .busy(led[15]));
  assign led[1:0] = u_fsm.state;        // a hierarchical name: the FSM's state on two LEDs
  assign led[14:2] = '0;
endmodule

tb.sv

module tb;
  reg clk = 1'b0, btnC = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i; reg [1:0] s;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  initial begin
    #1 btnC = 1'b1; #1 btnC = 1'b0; s = 2'd0;
    for (i = 0; i < 64; i = i + 1) begin
      sw = {15'd0, i[1] ^ i[3]}; #1
      if (!(led === {s == 2'd1, 13'd0, s})) begin $display("FAIL: state on led[1:0], busy on led[15] (step %0d, led=%h, want state %0d)", i, led, s); $finish; end
      tick;
      s = (s == 2'd0) ? (sw[0] ? 2'd1 : 2'd0) : (s == 2'd1) ? 2'd2 : 2'd0;
    end
    $display("PASS"); $finish;
  end
endmodule

previous: a course 'ready module' in netlist form in its own file ((* keep_hierarchy *), \<const0>, GND, LUT2), instantiated by the design
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