SystemVerilog probes · 57Vivado: supported

a course 'ready module' in netlist form in its own file ((* keep_hierarchy *), \<const0>, GND, LUT2), instantiated by the design

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. Vivado 2017.3 logs of the course's own example project (kept in a public CS223 repo): its keypad and seven-segment modules are the netlist-form files the course hands out. The synthesis log holds two runs; in the second the keypad module is the netlist form (LUT primitives pulled in from unisim_comp.v), 'done synthesizing module '<the keypad module>' (11#1)', 'Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.'. Implementation: 'write_bitstream completed successfully' (the logs do not say which synthesis run it used)

What does the open-source chain do with it?

since #28 rtl: PASS: iverilog refuses the design, 'ready.sv:20: error: Unknown module type: GND', and dewfpga sim goes on with 'ready.sv:20: note [sim-from-build]' (the simulation runs on the design as the build reads it, read by yosys' own reader, written back as Verilog and compiled with the testbench and yosys' cell models), then 'PASS'

Which error pages explain the messages?

• sim-from-build: Not an error: iverilog refused a construct in the design, so the testbench ran against the design as the build elaborates it, read by the reader the note names.

What is the probe's code?

From test/sv/57_ready_module_netlist.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  ready_xor u_x (.a(sw[0]), .b(sw[1]), .y(led[0]), .z(led[1]));   // a module the course hands out in netlist form (ready.sv)
  assign led[15:2] = sw[15:2];
endmodule

ready.sv

// A course "ready module": handed out in the form Vivado writes after synthesis (primitives, no RTL),
// the way the CS223 project files ship their keypad, stepper-motor and seven-segment drivers.
(* keep_hierarchy = "yes" *)
module ready_xor
   (a,
    b,
    y,
    z);
  input a;
  input b;
  output y;
  output z;

  wire \<const0> ;
  wire a;
  wire b;
  wire y;

  assign z = \<const0> ;
  GND GND
       (.G(\<const0> ));
  LUT2 #(
    .INIT(4'h6))
    y_INST_0
       (.I0(a),
        .I1(b),
        .O(y));
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {sw[15:2], 1'b0, sw[0] ^ sw[1]})) begin $display("FAIL: the ready module (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

previous: a typedef at file scope in a file of its own (types.sv holds only typedef enum ... state_t;), used by the design's module
next: a hierarchical name that reads a submodule's signal: assign led[1:0] = u_fsm.state;