SystemVerilog probes · 56bVivado: supported

a typedef at file scope in a file of its own (types.sv holds only typedef enum ... state_t;), used by the design's module

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 'Compilation Units' (p.270): 'Generally functions, tasks, parameter, nets, variables, and user defined types declared outside the module, interface, package or program come under the compilation unit scope', shared by files read without a library (read_verilog {test1.sv}, read_verilog {test2.sv})

What does the open-source chain do with it?

since #33 the CLI hands types.sv first: rtl: 'iverilog -g2012 -o top_sim types.sv design.sv tb.sv', PASS; bit: 'pnr ok: 2 LUT, 2 FF, clk 935.45 MHz (PASS at 100.00 MHz)'; netlist: the testbench prints PASS on the netlist, then 'EQV PASS: 262144 output bits compared, all equal'. Until 8 Oct 2026 the netlist stage failed in the harness, not the product: test/sv/eqv.sh put only package and interface files first and read design.sv before types.sv (a typedef-only file), so yosys stopped at the typedef name on line 2 and the eqv half failed; eqv.sh now reads a file without a module before the modules, as the product does. Before #33 (the CLI handed only files that hold a module): dewfpga sim stopped at line 2 with iverilog's Invalid module instantiation, dewfpga bit at the same syntax error. In which order Vivado compiles a file that holds only declarations is not in the guide

What is the probe's code?

From test/sv/56b_unit_typedef_file.

design.sv

module top(input logic clk, input logic btnC, input logic [15:0] sw, output logic [15:0] led);
  state_t state;                          // the type comes from types.sv
  always_ff @(posedge clk)
    if (btnC) state <= IDLE;
    else if (state == IDLE) state <= RUN;
    else if (state == RUN) state <= DONE;
    else state <= IDLE;
  assign led = {14'd0, state};
endmodule

types.sv

typedef enum logic [1:0] {IDLE, RUN, DONE} state_t;   // declared outside any module: the compilation unit

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  top dut(.clk(clk), .btnC(btnC), .sw(sw), .led(led));
  integer i;
  initial begin
    btnC = 1; tick; btnC = 0; #1
    for (i = 0; i < 9; i = i + 1) begin      // IDLE, RUN, DONE, IDLE, ...
      if (led !== 16'(i % 3)) begin $display("FAIL: after %0d edges led=%h, want %0d", i, led, i % 3); $finish; end
      tick; #1;
    end
    $display("PASS"); $finish;
  end
endmodule

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