SystemVerilog probes · 56Vivado: supported

typedef enum {S0, S1, S2} outside the module (compilation-unit scope), with the textbook's state names

Vivado: supported. The open-source chain: all four stages pass.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.10 'Compilation Units' (p.270): 'Generally functions, tasks, parameter, nets, variables, and user defined types declared outside the module, interface, package or program come under the compilation unit scope.'; Table 27 (p.285): 'User-defined types: Supported'

What does the open-source chain do with it?

builds since #3: the design is elaborated before yosys' xilinx cell library is read, so a file-scope enum item S0 no longer collides with a name in cells_sim.v (until #2 yosys stopped with enum item S0 already exists); 'pnr ok: 2 LUT, 2 FF', 'top.bit 2.2 MB', netlist PASS, 'EQV PASS: 196608 output bits compared, all equal'

What is the probe's code?

From test/sv/56_unit_scope_enum.

design.sv

typedef enum logic [1:0] {S0, S1, S2} statetype;   // declared outside the module (compilation-unit scope), textbook state names
module top(input logic clk, input logic btnC, output logic [15:0] led);
  statetype state;
  always_ff @(posedge clk)
    if (btnC) state <= S0;
    else case (state)
      S0: state <= S1;
      S1: state <= S2;
      default: state <= S0;
    endcase
  assign led = {14'b0, state};
endmodule

tb.sv

module tb;
  reg clk = 1'b0;
  reg btnC = 1'b0, btnU = 1'b0, btnD = 1'b0, btnL = 1'b0, btnR = 1'b0;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led; wire [6:0] seg; wire dp; wire [3:0] an;
  task tick; begin #5 clk = 1'b1; #5 clk = 1'b0; end endtask
  initial begin #200000 $display("FAIL: timeout"); $finish; end
  top dut(.clk(clk), .btnC(btnC), .led(led));
  initial begin
    btnC = 1; tick; btnC = 0;
    if (!(led === 16'd0)) begin $display("FAIL: reset to S0 (led=%h)", led); $finish; end
    tick; if (!(led === 16'd1)) begin $display("FAIL: S0 to S1 (led=%h)", led); $finish; end
    tick; if (!(led === 16'd2)) begin $display("FAIL: S1 to S2 (led=%h)", led); $finish; end
    tick; if (!(led === 16'd0)) begin $display("FAIL: S2 to S0 (led=%h)", led); $finish; end
    $display("PASS"); $finish;
  end
endmodule

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