SystemVerilog probes · 59Vivado: supported

$isunknown(sw) in a design (a real signal is never x, so it is 0)

Vivado: supported. The open-source chain: it stops before a bitstream.

What does Vivado do with it?

Supported. UG901 v2023.2 Ch.9 Table 21 (p.240): '$isunknown: Supported'

What does the open-source chain do with it?

dewfpga bit stops before yosys, no bitstream; a scan of the sources prints 'design.sv:2: ERROR [isunknown-in-design]: $isunknown in a design: on the board a signal is never x, so it is 0 there (and dewfpga sim shows 0); yosys folds it to the constant 1 instead, so the bitstream would not do what the simulation showed. Fix: remove it from the design; $isunknown belongs in the testbench.'

Which error pages explain the messages?

• isunknown-in-design: $isunknown in synthesizable code; a chip has no x, and yosys folds the call to a constant that differs from the simulation.

What is the probe's code?

From test/sv/59_isunknown.

design.sv

module top(input logic [15:0] sw, output logic [15:0] led);
  assign led[0] = $isunknown(sw);           // real switches are never x or z: always 0
  assign led[15:1] = sw[15:1];
endmodule

tb.sv

module tb;
  reg [15:0] sw = 16'h0000;
  wire [15:0] led;
  integer i;
  top dut(.sw(sw), .led(led));
  initial begin
    for (i = 0; i < 65536; i = i + 1) begin
      sw = i; #1
      if (!(led === {sw[15:1], 1'b0})) begin $display("FAIL: isunknown of a known value is 0 (sw=%h led=%h)", sw, led); $finish; end
    end
    $display("PASS"); $finish;
  end
endmodule

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