errors · bitdewfpga bit, the source scan before yosys

design.sv:2: ERROR [isunknown-in-design]: $isunknown in a design: on the board a signal is never x, so it is 0 there (and dewfpga sim shows 0); yosys folds it to the constant 1 instead, so the bitstream would not do what the simulation showed. Fix: remove it from the design; $isunknown belongs in the testbench.

design.sv:2: ERROR [isunknown-in-design]: $isunknown in a design: on the board a signal is never x, so it is 0 there (and dewfpga sim shows 0); yosys folds it to the constant 1 instead, so the bitstream would not do what the simulation showed. Fix: remove it from the design; $isunknown belongs in the testbench. https://nosey-dewdrop.github.io/dewfpga/errors/isunknown-in-design/

Why does it happen?

x exists only in simulation. Vivado and the simulator make $isunknown 0 on a driven signal; yosys makes it 1, so the two disagree, and the scan refuses it. A $isunknown under `ifndef SYNTHESIS is not reported.

What is the fix?

Move the check to the testbench:

if ($isunknown(led)) $error("led is x");

Which command prints it?

• dewfpga bit

Which probes in test/sv print this code?

• $isunknown(sw) in a design (a real signal is never x, so it is 0)

Every probe, with what Vivado does and what each stage does here: the probes, stage by stage.